Patents by Inventor An-Ming Lee

An-Ming Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12010826
    Abstract: A semiconductor structure includes a first transistor comprising a first gate structure over a first active region in a substrate. The semiconductor structure further includes a second active region in the substrate. The semiconductor structure further includes a first butted contact. The first butted contact includes a first portion extending in a first direction and overlapping the second active region, and a second portion extending from the first portion, wherein the second portion directly contacts each of a top surface and a sidewall of the first gate structure.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: You Che Chuang, Chih-Ming Lee, Hsin-Chi Chen, Hsun-Ying Huang
  • Patent number: 12009589
    Abstract: A terminal device includes a housing and a metal line that is disposed on an outer surface of the housing or is embedded in the housing, and the metal line is configured to receive or send an electromagnetic wave signal. The metal line acts as an antenna of the terminal device.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: June 11, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yu Chan Yang, Chien-Ming Lee, Hanyang Wang, Yi-Hsiang Liao, Lizhong Huang, Guangxiang Zhu, Bin Yu
  • Patent number: 12010811
    Abstract: A cable clip assembly for a computing device includes a primary clip with a primary surface between first and second primary ends. The first side extends in a first transverse direction from the first primary end, and the second side extends in the first transverse direction from the second primary end. Cable-receiving holes are arranged longitudinally between the first and second sides. A secondary clip has a secondary surface and is attached to the primary clip via the first and second sides. The secondary clip is movable relative to the primary clip between a cable installation position and a secured cable position, and is removably attached at one or more of the first and second sides. A compressible interface is attached to the primary surface, includes a flexible material that compresses when subjected to an installation force, and creates an airflow barrier in an installed position within the computing device.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: June 11, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chao-Jung Chen, Chih-Hsiang Lee, Chih-Ming Chen, Cheng-Hsiang Huang
  • Publication number: 20240186372
    Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.
    Type: Application
    Filed: February 12, 2024
    Publication date: June 6, 2024
    Inventors: Kai-Hsuan Lee, Bo-Yu Lai, Sai-Hooi Yeong, Feng-Cheng Yang, Yih-Ann Lin, Yen-Ming Chen
  • Publication number: 20240184195
    Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.
    Type: Application
    Filed: January 12, 2024
    Publication date: June 6, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh TIEN, Cheng-Hsuen CHIANG, Chih-Ming CHEN, Cheng-Ming LIN, Yen-Wei HUANG, Hao-Ming CHANG, Kuo-Chin LIN, Kuan-Shien LEE
  • Patent number: 12002863
    Abstract: A method includes forming a gate structure on a substrate, forming a seal spacer covering a sidewall of the gate structure, forming a sacrificial spacer covering a sidewall of the seal spacer, forming source/drain regions sandwiching a channel region that is under the gate structure, and depositing a contact etch stop layer covering a sidewall of the sacrificial spacer. The method further includes removing the sacrificial spacer to form a trench, wherein the trench exposes a sidewall of the contact etch stop layer and the sidewall of the seal spacer, and depositing an inter-layer dielectric layer, wherein the inter-layer dielectric layer caps the trench, thereby defining an air gap inside the trench.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Hsuan Lee, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Yen-Ming Chen
  • Patent number: 12002906
    Abstract: The present disclosure provides a semiconductor device and a semiconductor component. The semiconductor device includes an active structure, a ring-shaped semiconductor contact layer, a first electrode, and an insulating layer. The active structure has a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer located between the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer. The ring-shaped semiconductor contact layer is located on the second-conductivity-type semiconductor layer and having a first inner sidewall and a first outer sidewall. The first electrode has an upper surface and covers the ring-shaped semiconductor contact layer. The insulating layer covers the first electrode and the active structure and has a second inner sidewall and a second outer sidewall. The first inner sidewall is not flush with the second inner sidewall in a vertical direction.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: June 4, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Hao-Chun Liang, Wei-Shan Yeoh, Yao-Ning Chan, Yi-Ming Chen, Shih-Chang Lee
  • Patent number: 12002847
    Abstract: A power semiconductor device includes an epitaxial layer of a first conductivity type, a first doped region of a second conductivity type, a second doped region of the first conductivity type, a contact metal layer, a device electrode, a first termination electrode, and a second termination electrode. The epitaxial layer includes an active region and a termination region. The device electrode is located in a device trench in the active region, and is electrically isolated from the epitaxial layer and the contact metal layer. The first termination electrode is located in a first termination trench in the termination region and is electrically isolated from the epitaxial layer. The second termination electrode is located at a bottom of the first termination trench and is electrically isolated from the first termination electrode and the epitaxial layer. Both the first termination electrode and the second termination electrode are capable of being selectively floating.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: June 4, 2024
    Assignee: Invinci Semiconductor Corporation
    Inventors: Li-Ming Chang, Mei-Ling Chen, Hsu-Heng Lee
  • Publication number: 20240174105
    Abstract: An electric vehicle supply equipment that includes a form factor fitting a charging station including one interface for charging electric vehicles and at a second interface for powering street lighting. The first interface including a voltage for supporting level 2 charging. The electric vehicle supply equipment can also include an electrical box mounted to the structure with a form factor fitting the charging station that includes a connection to grid power. The electrical box includes an AC circuit, wherein a splitter provides for electrical communication from the AC circuit to the first and second interface, wherein the splitter provides for splitting the neutral and line cables of the AC input into a first branch that provides electrical communication to the first interface having the voltage for supporting level 2 charging, and a second branch that provides electrical communication to the second interface for powering the luminaire.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 30, 2024
    Inventors: Ming Li, Sally Lee, Tianzheng Jiang, Bruce Li
  • Publication number: 20240178271
    Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Yen-Ming Chen, Feng-Cheng Yang
  • Publication number: 20240174716
    Abstract: The present invention relates to transporter peptides that can bind to a transferrin receptor (TfR). The transporter peptides can be conjugated covalently or noncovalently to an effector agent to form a transporter peptide conjugate, or a nucleic acid encoding the transporter peptides and an effector agent is expressed to form a recombinant transporter peptide conjugate. The transporter peptide conjugate and the recombinant transporter peptide conjugate deliver the effector agent to a target by binding to a TfR. Binding of the transporter peptides to transferrin receptors on cells of a tissue barrier induces transcytosis of the cells, thereby transporting the transporter peptide conjugate across the tissue barrier. The transporter peptides can serve as a drug delivery system and used for treatment of central nervous system (CNS) diseases.
    Type: Application
    Filed: November 6, 2023
    Publication date: May 30, 2024
    Inventors: Jia-Ming CHANG, Yi-RU LEE
  • Patent number: 11996467
    Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Hsiang Hsu, Ting-Yeh Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11997933
    Abstract: In an embodiment, a device includes: a first metallization layer over a substrate, the substrate including active devices; a first bit line over the first metallization layer, the first bit line connected to first interconnects of the first metallization layer, the first bit line extending in a first direction, the first direction parallel to gates of the active devices; a first phase-change random access memory (PCRAM) cell over the first bit line; a word line over the first PCRAM cell, the word line extending in a second direction, the second direction perpendicular to the gates of the active devices; and a second metallization layer over the word line, the word line connected to second interconnects of the second metallization layer.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Shao-Ming Yu, Yu Chao Lin
  • Publication number: 20240172434
    Abstract: A semiconductor device includes a stacked gate structure, a plurality of stacks and a first conductive layer. The stacks are disposed aside the stacked gate structure and arranged along both a first direction and a second direction perpendicular to the first direction, wherein the stacks are extended continuously along the first direction and segmented in the second direction. The first conductive layer is disposed between segmented portions of the stacks along the second direction, wherein top surfaces of the segmented portions of the stacks are higher than a top surface of the first conductive layer.
    Type: Application
    Filed: January 31, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
  • Publication number: 20240170211
    Abstract: A metal electrode of a ceramic capacitor and a method of forming the same are provided. The method includes mixing metal powders and a barium titanate organic-precursor to obtain precursor powders; adding an adhesive to the precursor powders to obtain a metal slurry; performing a molding process to the metal slurry to obtain a film material; performing a binder burn-out process to the film material to obtain a degumming film; and performing a sintering process to the degumming film to obtain the metal electrode. By mixing specific amount of barium titanate organic-precursor with the metal powders, the barium titanate metallic organic-precursor can be transformed to barium titanate in the following process, and barium titanate can be dispersed between the metals homogeneously. Therefore, electrode continuity can be increased.
    Type: Application
    Filed: February 24, 2023
    Publication date: May 23, 2024
    Inventors: Hsing-I HSIANG, Fu-Su YEN, Chi-Yuen HUANG, Chun-Te LEE, Kai-Hsun YANG, Shih-Ming WANG
  • Publication number: 20240170341
    Abstract: Semiconductor devices and methods of manufacture are discussed. In an embodiment, a method of manufacturing a semiconductor device includes: forming first nanostructures from a first material over a substrate; forming second nanostructures from a second material different from the first material over the substrate, wherein the first nanostructures and the second nanostructures alternate vertically above the substrate; removing the first nanostructures; after the removing the first nanostructures forming an interposer in between the second nanostructures; after the forming the interposer forming a first source/drain region over the substrate and in direct physical contact with the second nanostructures; and removing the interposer exposing surfaces of each of the second nanostructures.
    Type: Application
    Filed: January 10, 2023
    Publication date: May 23, 2024
    Inventors: Yu-Ming Chen, Tsung-Lin Lee, Chia-Ho Chu, Sung-En Lin, Sen-Hong Syue
  • Publication number: 20240166498
    Abstract: Disclosed is a responsive platform, which includes a polymer-grafted nanopillar array, cargo-containing entities, first conjugatable moieties, and second conjugatable moieties. The polymer-grafted nanopillar array includes thermoresponsive polymer brushes grafted onto surfaces of nanopillars, and the cargo-containing entities are attached to the thermoresponsive polymer brushes through non-covalent association between the first conjugatable moieties and the second conjugatable moieties. Accordingly, the cargo-containing entities can be released from the nanopillar array for cellular uptake in a controlled manner by applying thermal stimulus.
    Type: Application
    Filed: November 7, 2022
    Publication date: May 23, 2024
    Inventors: Hsiao-hua YU, Hsien-Ming LEE, Bhaskarchand Sureshchand Gautam
  • Patent number: 11990378
    Abstract: An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Yuan Chen, Jui-Ping Lin, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11989966
    Abstract: A method for forming semiconductor devices includes providing a substrate with a conductive pad formed thereon; forming a transparent structure over the substrate, wherein the transparent structure includes a plurality of collimating pillars adjacent to the conductive pad; forming a light-shielding structure over the plurality of collimating pillars and the conductive pad; performing a cutting process to remove one or more materials directly above the conductive pad, while leaving remaining material to cover the conductive pad, wherein the material includes a portion of the light-shielding structure; and performing an etching process to remove the remaining material to expose the conductive pad.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: May 21, 2024
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsin-Hui Lee, Han-Liang Tseng, Jiunn-Liang Yu, Kwang-Ming Lin, Yin Chen, Si-Twan Chen, Hsueh-Jung Lin, Wen-Chih Lu, Chih-Hsien Chen
  • Patent number: 11986763
    Abstract: A remote control system for gas detection and purification is disclosed and includes a remote control device, a gas detection module and a gas purification device. The remote control device includes a gas inlet and a gas outlet. The gas detection module is disposed in the remote control device and in communication with the gas outlet to detect the gas located in an indoor space. The gas detection module provides and outputs a gas detection datum, and the remote control device transmits an operation command via wireless transmission. The gas purification device is disposed in the indoor space and receives the operating instruction transmitted from the remote control device to be operated. When the gas purification device is under the activated state, the gas in the indoor space is purified, and the purification operation mode of the gas purification device is adjusted according to the first gas detection datum.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 21, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Yung-Lung Han, Chi-Feng Huang, Chun-Yi Kuo, Yang Ku, Chang-Yen Tsai, Wei-Ming Lee