Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.

Abstract: For a given application, increasing the size of a cache is beneficial up to a certain point and the number of hits does not increase significantly with a greater cache size. This disclosure provides a method to determine a miss ratio curve, for a cache having data blocks with a time-to-live. A hashed value of a data block's key address can be used to generate a 2D HLL counter for storing expiry times of the data blocks. The 2D HLL counter can be converted to a 1D array, from which a stack distance can be calculated. A frequency distribution of stack distances can then be converted into a miss ratio curve, from which an appropriate cache size can be selected.

Abstract: Oral care based imaging computer-implemented systems and methods for determining perceived attractiveness of a facial image portion of at least one person depicted in a digital image. The method has the following steps: a) obtaining a digital image comprising at least one oral feature of at least one person, wherein the digital image includes a facial image portion of the at least one person, the facial image portion having both positive and negative attributes as defined by pixel data of the digital image; b) analyzing the facial image portion; c) generating an Attractiveness Score indicative of a perceived attractiveness of the facial image portion based on the analyzed facial image portion in the obtained digital image; d) further generating an image description that identifies at least one area in said facial image portion based on the Attractiveness Score; and e) presenting the image description to a use.

Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: A capability reporting method and a modem chip performing the same are provided. The capability reporting method includes the following steps. A capability enquiry message is received from a network. A plurality of weightings for a serving Radio Access Technology (RAT) and at least one non-serving RAT are determined. The weighting for the at least one non-serving RAT is downgraded. A plurality of capability information for the serving RAT and the non-serving RAT are composed according to the weightings. The size of the capability information for the at least one non-serving RAT is reduced. The capability information for the serving RAT and the capability information for the at least one non-serving RAT are combined to obtain a capability report message. The capability report message is replied to the network.

Abstract: A test strip for sampling a bodily fluid may include multiple layers of a substrate material, an adhesive between at least some of the multiple layers, and a microfluidic channel formed between at least some of the multiple layers. The test strip may further include multiple electrodes on one of the multiple layers, positioned and partially exposed within the microfluidic channel, an additional material positioned at or near an entrance to the microfluidic channel, to selectively limit the flow of at least one of bubbles or debris into the microfluidic channel, and at least one exit port in at least one of the multiple layers to allow for release of pressure from the test strip. In some embodiments, the test strip is a saliva analysis test strip. In some embodiments, the test strip includes multiple exit ports to prevent blockage of sample flow.

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Abstract: An electronic includes an electronic element, an encapsulation layer surrounding the electronic element, a first circuit structure, a second circuit structure and a connecting structure. The encapsulation layer has a top surface, a bottom surface and an opening, wherein a sidewall of the opening connects the top surface and the bottom surface. The first circuit structure is disposed at the top surface of the encapsulation layer. The second circuit structure is disposed at the bottom surface of the encapsulation layer. The connecting structure is disposed in the opening, wherein the electronic element is electrically connected to the second circuit structure through the first circuit structure and the connecting structure. The connecting structure includes a first sub layer and a second sub layer, the first sub layer is located between the encapsulation layer and the second sub layer, and the first sub layer covers the sidewall of the opening.

Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The UE receives, from a source cell, a conditional handover (CHO) command configuring the UE to perform a CHO procedure to handover to a target cell in response to satisfying a CHO condition. The UE receives, from the source cell after receiving the CHO command, a handover (HO) command configuring the UE to perform a HO procedure to handover to the target cell. The UE determines whether the UE has started the CHO procedure prior to receiving the HO command. The UE, in response to determining that the UE has started the CHO procedure prior to receiving the HO command, discards the HO command and continues with the CHO procedure.

Abstract: Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).

Abstract: A method of forming a semiconductor device includes forming a photoresist layer over a mask layer, patterning the photoresist layer, and forming an oxide layer on exposed surfaces of the patterned photoresist layer. The mask layer is patterned using the patterned photoresist layer as a mask.

Abstract: A discontinuous transmission (DTX) information transmission method is provided. The DTX information transmission method may include the following steps. A processor of an apparatus may determine whether to enter a DTX mode. A transceiver of the apparatus may transmit DTX information to a network node in response to determining to enter the DTX mode.

Abstract: An impeller includes a hub and a plurality of blades. The blades are arranged around the hub, and each blade includes a leading edge, a blade tip, a root portion, a trailing edge, a windward side and a leeward side. The windward side including a first turning point and a second turning point, a first vertical height difference is formed from the blade tip to the first turning point, and a second vertical height difference is formed from the first turning point to the second turning point, and the first vertical height difference is greater than the second vertical height difference. The impeller apparently reduces the noise.

Abstract: A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

Abstract: A connector assembly includes a base, a wire unit, and a wire fixing unit. The base includes a body and two side wings. The two side wings are respectively rotatably connected to two opposite sides of the body, and each of the side wings includes a first fixing portion. The wire unit is located between the two side wings. The wire unit includes a connection seat disposed in the body, and various wires disposed in the connection seat and protruding from one side of the connection seat. The wire fixing unit includes two second fixing portions and various through holes, in which the through holes are located between the two second fixing portions, the two first fixing portions respectively clamp the two second fixing portions, and the wires correspondingly pass through the through holes.

Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

Abstract: Disclosed are a source driver and a method of detecting crack of a display panel. A source driver may comprise a first circuit configured to apply first data to data lines connected to sub-pixels of a display panel to charge a first driving voltage; and a second circuit formed on the display panel that applies the first driving voltage to a detection line formed on the display panel to detect the presence of cracks in the display panel based on the illumination status of the sub-pixels, wherein the detection line includes a first detection node and a second detection node formed on one side of the display panel along its extension direction, wherein the first detection node is connected to data lines of the first and third sub-pixels, and wherein the second detection node is connected to data line of the second sub-pixel.

Abstract: A method of forming a semiconductor structure includes the following operations. A semiconductor epitaxial layer is formed on a first semiconductor substrate. A first side of the semiconductor epitaxial layer is adhered to a transfer substrate by an adhesive layer covering the first side of the semiconductor epitaxial layer. The semiconductor epitaxial layer and the first semiconductor substrate are turned over by the transfer substrate. The first semiconductor substrate is removed to expose a second side of the semiconductor epitaxial layer opposite to the first side. A first semiconductor doped region is formed on the second side of the semiconductor epitaxial layer. After the first semiconductor doped region is formed, the adhesive layer and the transfer substrate are removed.