Abstract: An imaging optical lens assembly includes five lens elements. The five lens elements in order from an object side to an image side along an optical path are a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. Each of the five lens elements has an object-side surface facing the object side and an image-side surface facing the image side. The first lens element has positive refractive power, the second lens element has negative refractive power and the third lens element has negative refractive power. With specific conditions being satisfied, the imaging optical lens assembly can be miniaturized while providing good image quality.

Abstract: A fracturing apparatus is provided. The fracturing apparatus includes a plunger pump, a transmission shaft, a main motor, an oil pipe, a first radiator and a noise reduction cabin. The main motor is spaced apart from the plunger pump, the plunger pump is connected with the main motor through the transmission shaft; the oil pipe is configured to be connected with the plunger pump; the first radiator is spaced apart from the plunger pump, the first radiator is configured to dissipate heat from oil in the oil pipe, the main motor, the first radiator and at least part of the oil pipe are all located inside the noise reduction cabin, and the plunger pump is located outside the noise reduction cabin.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.

Abstract: Disclosed herein are related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: A memory device includes a first transistor. The first transistor includes one or more first semiconductor nanostructures spaced apart from one another along a first direction. Each of the one or more first semiconductor nanostructures has a first width along a second direction perpendicular to the first direction. The memory device also includes a second transistor coupled to the first transistor in series. The second transistor includes one or more second semiconductor nanostructures spaced apart from one another along the first direction. Each of the one or more second semiconductor nanostructures has a second, different width along the second direction.

Abstract: A semiconductor device includes a ferroelectric field-effect transistor (FeFET), wherein the FeFET includes a substrate; a source region in the substrate; a drain region in the substrate; and a gate structure over the substrate and between the source region and the drain region. The gate structure includes a gate dielectric layer over the substrate; a ferroelectric film over the gate dielectric layer; and a gate electrode over the ferroelectric film.

Abstract: A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

Abstract: An antifuse structure and IC devices incorporating such antifuse structures in which the antifuse structure includes an dielectric antifuse structure formed on an active area having a first dielectric antifuse electrode, a second dielectric antifuse electrode extending parallel to the first dielectric antifuse electrode, a first dielectric composition between the first dielectric antifuse electrode and the second dielectric antifuse electrode, and a first programming transistor electrically connected to a first voltage supply wherein, during a programming operation a programming voltage is selectively applied to certain of the dielectric antifuse structures to form a resistive direct electrical connection between the first dielectric antifuse electrode and the second dielectric antifuse electrode.

Abstract: A diffractive optical element and method for fabricating the diffractive optical element are provided. The diffractive optical element includes a substrate, a first diffractive structure layer and a second diffractive structure layer. The substrate has a first surface and a second surface opposite to the first surface. The first diffractive structure layer is disposed on the first surface of the substrate. The second diffractive structure layer is disposed on the second surface of the substrate. In the method for fabricating the diffractive optical element, at first, the substrate is provided. Then, a first glue material layer/first semiconductor layer is formed and patterned on the first surface of the substrate. Thereafter, a second glue material layer/second semiconductor layer is formed and patterned on the second surface of the substrate.

Abstract: A slickline that includes both electrically conductive and fiber optic capacity. The slickline includes a fiber optic thread or bundle of threads that may be surrounded by an electrically conductive member such as split half shells of copper elements. Further, these features may be disposed in a filler matrix so as to provide a cohesiveness the core of the slickline. So, for example, the line may be more effectively utilized in downhole applications such as coiled tubing operations, without undue concern over collapse or pinhole issues emerging in the line.

Abstract: A mobile device with high radiation efficiency includes a ground element, a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, a dielectric substrate, a speaker body, and a cable. The first radiation element and the fourth radiation element are coupled to the ground element. The second radiation element and the third radiation element are coupled to a feeding point. An antenna structure is formed by the first radiation element, the second radiation element, the third radiation element, and the fourth radiation element. The speaker body has a first vertical projection on the dielectric substrate, and the first vertical projection at least partially overlaps the third radiation element. The cable is coupled to the speaker body. The cable has a second vertical projection on the dielectric substrate, and the second vertical projection does not overlap the antenna structure at all.

Abstract: A method of forming a storage cell includes: forming a transistor on a semiconductor substrate; forming a plurality of fuses in at least one conductive layer on the semiconductor substrate to couple a connecting terminal of the transistor; forming a bit line to couple the plurality of fuses; and forming a word line to couple a control terminal of the transistor.

Abstract: A method of operating a memory circuit includes turning on a first programming device and turning on a first selection device thereby causing a first current to flow through a first fuse element. The first fuse element is coupled between the first selection device and the first programming device. The method further includes turning off a second programming device and turning off a second selection device, and blocking the first current from flowing through a second fuse element that is coupled between the second selection device and the first programming device.

Abstract: The present invention may disclose a turbine fracturing equipment, including a transporter, a turbine engine, a reduction gearbox, a transmission mechanism and a plunger pump, wherein an output end of the turbine engine may be connected to one end of the reduction gearbox, the other end of the reduction gearbox may be connected to the plunger pump through a transmission mechanism; the transporter may be used to support the turbine engine, the reduction gearbox, the transmission mechanism and the plunger pump; the transporter may include a chassis provided with a transport section, a bearing section and a lapping section which may be connected in sequence; while the turbine fracturing equipment may be in a working state, the bearing section can contact with the ground, while the turbine fracturing equipment may be in a transport state, the bearing section may not contact with the ground.

Abstract: A memory cell includes: a first transistor, having a first diffusion region coupled to a bit line and a first gate electrode coupled to a first word line; a second transistor, having a second diffusion region coupled to the bit line and a second gate electrode coupled to a second word line; and a third transistor, having a third diffusion region coupled to a fourth diffusion region of the first transistor, a fifth diffusion region coupled to a sixth diffusion region of the second transistor, and a third gate electrode coupled to a third word line; wherein the first transistor is arranged to have a first threshold voltage, the second transistor is arranged to have a second threshold voltage, and the second threshold voltage is different from the first threshold voltage.

Abstract: A layout method includes: forming a layout structure of a memory array having first and second rows, each including a plurality of storage cells, wherein at least one of the storage cells includes a fuse; disposing a word line between the first and second rows; disposing a plurality of control electrodes across the word line for connecting the storage cells of the first row and the storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.

Abstract: An imaging lens includes a first lens with a negative refractive power, a second lens with a positive refractive power, a third lens with a positive refractive power and a fourth lens with a refractive power arranged in order from a first side to a second side, and an aperture stop is disposed between the first lens and the third lens. The first lens, the second lens, the third lens and the fourth lens are made from glass, a total number of lenses with refractive powers in the imaging lens is less than 5, the second lens and the third lens are aspheric glass lenses, and a full field of view of the imaging lens is greater than 120 degrees.

Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

Abstract: An integrated circuit includes a front-side horizontal conducting line in a first metal layer, a front-side vertical conducting line in a second metal layer, a front-side fuse element, and a backside conducting line. The front-side horizontal conducting line is directly connected to the drain terminal-conductor of a transistor through a front-side terminal via-connector. The front-side vertical conducting line is directly connected to the front-side horizontal conducting line through a front-side metal-to-metal via-connector. The front-side fuse element having a first fuse terminal conductively connected to the front-side vertical conducting line. The backside conducting line is directly connected to the source terminal-conductor of the transistor through a backside terminal via-connector.