Abstract: An apparatus comprising detection logic configured to detect a loop among a set of instructions, the loop comprising one or more instructions of a first type of instruction and a second type of instruction and a co-processor configured to execute the loop detected by the detection logic, the co-processor comprising an instruction queue. The apparatus further comprises fetch logic configured to fetch instructions; decode logic configured to determine instruction type; a processor configured to execute the loop detected by the detection logic, wherein the loop comprises one or more instructions of the first type of instruction, and an execution unit configured to execute the loop detected by the detection logic.

Abstract: Systems and methods are disclosed to process a semiconductor substrate by fabricating a first layer on the substrate using semiconductor fabrication techniques; fabricating a second layer above the first layer having one or more NANO-bonding areas; self-assemblying one or more NANO-elements; and bonding the NANO-elements to the NANO-bonding areas.

Abstract: A storage virtualization controller for transferring data between a host and a storage device at a wire-speed data transfer rate. A downstream processing element adapted for connection to the storage device is configurable coupled to an upstream processing element adapted for connection to the host. A central processing element coupled to the upstream processing element grants permission to the upstream processing element to transfer the data at the wire-speed rate without further involvement by the central processing element.

Abstract: Methods, systems, and articles of manufacture that may be used to attach annotations to a particular view of data described by the annotation are provided. The annotation may be attached in a manner that allows the annotation to be viewed when subsequent views having at least some visible cells in common with the annotated view are displayed. An annotation created for a view of data may be stored with links to each cell visible in the view. When a predetermined set of cells visible in the annotated view are subsequently displayed in another view, the annotation may be retrieved via the cell links and an indication of the annotation may be provided.

Abstract: Techniques for sending routing data include sending first routing data in a first multicast packet to a number N of adjacent nodes. It is determined whether different routing data is ready to be sent in a different multicast packet. If so, then a number M of adjacent nodes from which acknowledgment messages have been received, and whether M exceeds a threshold, is determined. If so, then a Conditional-Receive (CR) method is invoked in which a multicast message is sent which identifies each of a number L=N?M of laggard adjacent nodes. The laggard adjacent nodes are thus notified to ignore the different multicast packet. If it is determined that M does not exceed the threshold, then additional acknowledgement messages are received while waiting until M does exceed the threshold before the CR method is invoked. The threshold is greater than or equal to 1.

Abstract: For a database query that defines a plurality of separate snowflake schemas, a query optimizer computes separately for each of the snowflake schemas a logical access plan for obtaining from that schema's tables a respective record set that includes the data requested from those tables by that query. The query optimizer also computes a logical access plan for obtaining the query's results from the record sets in which execution of the logical access plans thus computed will result.

Abstract: Switching between communication ports of a notebook is typically accomplished using an off-chip local area network (LAN) switch or an off-chip high speed analog multiplexer. This off-chip component is disadvantageous for several reasons, including: added cost of an additional component; increased overall power consumption because transmit amplitude loss; and reduced cable reach and link performance due to hybrid mismatch and signal distortions. To reduce cost and preserve electrical and networking performance, an integrated switch is provided to multiplex signals of a networking communication chip to multiple network paths.

Abstract: The present invention is directed to methods and systems for scaling receive protocol processing by allowing the network load from a network adapter to be balanced across multiple CPUs based on RSS and/or QoS traffic classification techniques.

Abstract: Techniques for synchronizing routing data include determining whether conditions are satisfied for one-way transfer with an adjacent router. If it is determined that conditions are satisfied for one-way transfer of routing table data with the adjacent router, then a refresh-notice message is sent from the initiating router to the adjacent router. The refresh-notice message includes data that indicates a particular direction for transfer of routing table data. If the particular direction is inbound, then a copy of an adjacent routing table is received without sending a copy of the initiating router's own routing table. If the particular direction is outbound, then a copy of the own routing table is sent without receiving a copy of the adjacent routing table.

Abstract: Some embodiments of the present invention provide a method and system for correlating information regarding an interactive communication. A session application record is provided to store information of a session that represents an interactive communication that is at least between two endpoints. An application programming interface (API) is provided for users to create and manipulate session application records. Application specific data or customized data can be stored with the session application record using a tag that includes a name and value pair. One session application record can be associated with another session application record by using a relation. Any information that is gathered during a session can be accessible even when one of the endpoints is replaced by another endpoint.

Abstract: The invention is directed to pyrro[1,2-b]pyridazinone compounds and pharmaceutical compositions containing such compounds that are useful in treating infections by hepatitis C virus.

Abstract: Embodiments of the present invention relate to a method and mechanism for managing location information in a wireless portal environment. The method consists of acquiring the location information from a user's location-enabled wireless device which is in communication with a wireless network, storing the location information in a storage device in the wireless network, retrieving the location information from the storage device in the wireless network, and disseminating the location information to a client which is also in communication with the wireless network. A client can be any type of network presence that is enabled to provide services that are enhanced with knowledge of a user's physical location in a wireless portal environment. The location information can be geophysical information derived from global positioning system (GPS) or any other location-specific information from a suitable source.

Abstract: What is provided in one embodiment is a method and apparatus for confirming that one or more items in a universe of items fall within specified tolerances. In another embodiment various methods for determining best fit between items in a universe of items is provided.

Abstract: According to one embodiment, a phase-locked loop (PLL) device includes test circuitry for entering/exiting a test mode upon receiving a particular pulse train at a reference clock input of the PLL. In addition, exemplary methods are provided herein for entering a test mode and detecting loop filter leakage within the PLL. The methods described herein are performed without the use of a dedicated test pin.

Abstract: Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.

Abstract: An SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode is provided. In one embodiment, the SRAM device includes a hierarchical grouping of memory cells of memory cells and biasing circuitry, coupled to the hierarchical grouping of memory cells, configured to bias a subset of the set based on a memory address associated therewith. In another embodiment, a method includes receiving a memory address associated with the hierarchical grouping of memory cells and biasing a subset of the hierarchical grouping of memory cells based on the memory address.

Abstract: A processor (1700) including a pipeline (1710, 1740) having a fetch pipeline (1710) with branch prediction circuitry (1840) to supply respective predicted taken target addresses for branch instructions, an execution pipeline (1740) with a branch execution circuit (1870), and storage elements (in 1860) and control logic (2350) operable to establish a first-in-first-out (FIFO) circuit (1860) with a write pointer WP1 and a read pointer RP1. The control logic (2350) is responsive to the branch prediction circuitry (1840) to write a predicted taken target address to a storage element (in 1860) identified by the write pointer (WP1) and the predicted taken target address remains stationary therein. The FIFO circuit (1860) bypasses a plurality of pipestages between the branch prediction circuitry (1840) and the branch execution circuit (1870). The control logic (2350) is operable to read a predicted taken target address (PTTPCA) from a storage element (in 1860) identified by the read pointer RP1.

Abstract: A multi-operational amplifier system comprises a plurality of operational amplifiers and a controller to configure the plurality of operational amplifiers. The operational amplifiers may be selectively configured to operate individually or in combination with other of the operational amplifiers. The operational amplifiers may have different common node inputs. In one aspect, the different inputs may be selected from groups of PMOS, N-type NMOS and NZ NMOS inputs. The operational amplifiers may include the different inputs that are arranged as differential pairs.

Abstract: A voltage control circuit includes a first transistor coupled to a first voltage supply terminal having a first voltage, a second transistor coupled to the first transistor and a node, a third transistor coupled to a second voltage supply terminal and the node, wherein the second voltage supply terminal has a second voltage and the node is at a voltage selected from the group consisting of the first voltage and the second voltage, and a fourth transistor coupled to the node.

Abstract: A method for fluxing a solder comprises applying to the solder a fluxing agent in which the fluxing agent is a compound having (i) an aromatic ring, (ii) at least one —OH, —NHR (where R is hydrogen or lower alkyl), or —SH group (iii) an electron-withdrawing or electron-donating substituent on the aromatic ring, and (iv) no imino group.