Abstract: Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a decoder may use the same circuitry to perform updating of edge messages with respect to bit nodes as well as updating of edge messages with respect to check nodes in the context of decoding LDPC coded signals. In addition, several very efficient architectures are presented to performing check node processing that involves the updating of edge messages with respect to check nodes. One embodiment performs check node processing using min** (min-double-star) processing in conjunction with min**? (min-double-star-minus) processing. Another embodiment performs check node processing using min†† (min-double-dagger) processing in conjunction with min†? (min-dagger-minus) processing. In addition, a single FIFO may be implemented to service a number of macro blocks in a parallel decoding implementation.

Abstract: The present invention relates generally to the field of anti-infective, anti-proliferative, anti-inflammatory, and prokinetic agents. More particularly, the invention relates to a family of compounds having both a biaryl moiety and at least one heterocylic moiety that are useful as such agents.

Abstract: A liquid extraction cleaner comprises a solution dispensing system, a liquid recovery system, and an agitation brush assembly. The solution dispensing system includes a cleaning solution supply tank affixed to the cleaner and fluidly connected to a solution spray nozzle through a trigger-operated manual solution spray pump. The supply conduit interconnecting the cleaning fluid supply tank and the spray nozzle traverses a passage formed integrally with the air-liquid separator housing, spray nozzle being mounted in the passage at a front portion of the cleaner. The liquid recovery system includes a air-liquid separator fluidly connected with a suction nozzle and a suction source for drawing liquid and debris into the air-liquid separator, and a recovery tank releasably mounted to the air-liquid separator for collecting recovered liquid. The agitation brush assembly is mounted in a lower forward portion of the cleaner for contact with a surface being cleaned.

Abstract: Efficient design to implement LDPC decoder. The efficient design presented herein provides for a solution that is much easier, smaller, and has less complexity than other possible solutions. The use of a ping-pong memory structure (or pseudo-dual port memory structure) in conjunction with a metric generator near the decoder's front end allows parallel bit/check node processing. An intelligently operating barrel shifter operates with a message passing memory that is operable to store updated edges messages with respect to check nodes as well as updated edges messages with respect to bit nodes. Using an efficient addressing scheme allows the same memory structure to store the two types of edges messages with respect to bit nodes: (1) corresponding to information bits and (2) corresponding to parity bits. In addition, an intelligently designed hardware macro block may be instantiated a number of times into the decoder design to support ever greater design efficiency.

Abstract: A method and system for integrity certification and verification in a computer environment based on characteristics and behaviors of one or more applications, systems or system components as compared with a profile of characteristics and behaviors, including determining a behavior integrity profile (BIP) specifying characteristics and behaviors of one or more applications, systems or system components; determining based on the BIP whether or not characteristics and behaviors of one or more applications, systems or system components are compliant with characteristics and behaviors defined in a behavior integrity profile specification; and determining access rights to the one or more applications, systems or system components based on the step of determining the compliance.

Abstract: Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders. A novel approach is presented by which the front end design of device capable to decode LDPC coded signals facilitates parallel decoding processing of the LDPC coded signal. The implementation of the front end memory management in conjunction with the implementation of a metric generator operate cooperatively lend themselves for very efficient parallel decoding processing of LDPC coded signals. There are several embodiments by which the front end memory management and the metric generator may be implemented to facilitate this parallel decoding processing of LDPC coded signals. This also allows for the decoding of variable code rate and/or variable modulation signals whose code rate and/or modulation varies as frequently as on a block by block basis (e.g., a block may include a group of symbols within a frame).

Abstract: An evaporative cooler apparatus is disclosed. The evaporative cooler apparatus comprises a bottom and a top, where the bottom and the top are identically dimensioned, and where the top and the bottom are interchangeable. The evaporative cooler apparatus further comprises a U-shaped vertical element disposed between the bottom and the top, where that vertical element comprises a porous material. The evaporative cooler apparatus does not comprise one or more metal or plastic sides formed to include a plurality of apertures.

Abstract: Fast min*? (min-star-minus) or max*? (max-star-minus) circuit in LDPC (Low Density Parity Check) decoder. A novel and efficient approach by which certain of the calculations required to perform check node processing within various types of decoders is presented. The functionality and architectures presented herein are applicable to LDPC decoders and may also be employed within other types of decoders that are operable to decode other types of coded signals as well. The parallel and sometimes simultaneous calculation and determination of certain parts of the overall resultant of the max*? and/or min*? processing allows for very fast operation when compared to prior art approaches.

Abstract: Optical components may be integrated into planar light circuits. For example, thin film filters may be integrated through trenches in planar light circuits to achieve demultiplexing of at least two multiplexed optical wavelengths. An optical waveguide may be interfaced with a laser or a light detector through a mode converter formed as a trench in the planar light circuit. The mode converter may have a curved surface to achieve mode conversion.

Abstract: A vinyl French nail kit includes a brush applicator and a predetermined quantity of a nail glue for being applied by the brush applicator to a select area on a nail. The kit further includes at least one flexible vinyl strip positionable onto a nail and over the nail glue. The nail kit further includes a predetermined quantity of a bonding agent for securing at least one flexible vinyl strip to a nail. A user applies the bonding agent via the brush applicator over the nail and over at least one vinyl strip for securing same to a nail. The nail kit further includes a nail file for removing the opposed end portions of at least one vinyl strip. The nail kit further includes a predetermined quantity of a finishing agent for application by a user onto at least one vinyl strip and associated nail via the brush applicator.

Abstract: A system and method for processing data (e.g., encoded audio data in an audio decoder). Various aspects of the present invention may comprise a first memory module comprising a first software module and a second software module. A signal-processing module may comprise a processor and local memory. A first data segment may be received, and the processor may identify the first software module for processing the first data segment. The first software module may be transferred to the local memory and executed by the processor to process the first data segment. A second data segment may be received, and the processor may identify the second software module for processing the second data segment. The second software module may be transferred to the local memory in memory space formerly occupied by the first software module. The processor may then utilize the second software module to process the second data segment.

Abstract: This application discloses a microelectromechanical (MEMS) switch apparatus comprising an anchor attached to a substrate and an electrically conductive beam attached to the anchor and in electrical contact therewith. The beam comprises a tapered portion having a proximal end and a distal end, the proximal end being attached to the anchor, an actuation portion attached to the distal end of the tapered portion, a tip attached to the actuation portion, the tip having a contact dimple thereon. The switch apparatus also includes an actuation electrode attached to the substrate and positioned between the actuation portion and the substrate. Additional embodiments are also described and claimed.

Abstract: A high voltage generator provides high voltage signals with different regulated voltage levels. A charge pump generates the high voltage, and includes a quadrature phase forward and backward Vt-canceling high-voltage self-biasing charge pump with a powerup-assist diode. A high voltage series regulator generates the high voltage supply levels, and includes slew rate enhancement and trimmable diode regulation. A nested loop regulator eliminates shunt regulation.

Abstract: A memory structure that includes a first electrode, a second electrode, a third electrode, a control element of a predetermined device type disposed between the first electrode and the second electrode, and a memory storage element of the predetermined device type disposed between the second electrode and the third electrode. The memory storage element has a cross-sectional area that is less than a cross-sectional area of the control element.

Abstract: Method and system for querying a collection of Unstructured or semi-structured documents to identify presence of, and provide context and/or content for, keywords and/or keyphrases. The documents are analyzed and assigned a node structure, including an ordered sequence of mutually exclusive node segments or strings. Each node has an associated set of at least four, five or six attributes with node information and can represent a format marker or text, with the last node in any node segment usually being a text node. A keyword (or keyphrase) is specified, and the last node in each node segment is searched for a match with the keyword. When a match is found at a query node, or at a node determined with reference to a query node, the system displays the context and/or the content of the query node.

Abstract: A product for dust control and freeze control, wherein the product comprises a mixture of from about 45 to about 90 weight percent of glycerin, from about 5 to about 50 weight percent of water and from about 2 to about 15 weight percent of a water soluble salt is described and claimed. The product may be diluted with about 10 to about 400 weight percent of water for use, based on the amount of the product present. The freezing point of the product for example may be about ?35° C. The product may be synthesized using commercially available chemicals, or it may be derived from vegetable oils, or it may be a byproduct from a biodiesel manufacturing process of forming fatty acid esters from vegetable oils.

Abstract: A catheter for ablating body tissue of the interior regions of the heart includes a handle assembly, a shaft, and a distal tip section coupled to the distal end of the shaft. The distal tip section has a non-compliant and non-porous cap that has a tubular wall that defines a bore, and an ablation element that is housed inside the bore and spaced apart from the wall of the cap.

Abstract: A concentrated product for dust control and freeze control, wherein the concentrated product comprises a mixture of from about 45 to about 90 weight percent of glycerin, from about 5 to about 50 weight percent of water and from about 2 to about 15 weight percent of a water soluble salt is described and claimed. The concentrated product may be diluted with about 10 to about 400 weight percent of water for use, based on the amount of the concentrated product present. The freezing point of the concentrated product is about -35° C. The concentrated product may be synthesized using commercially available chemicals, or it may be derived from vegetable oils, or it may be a byproduct from a biodiesel manufacturing process of forming fatty acid esters from vegetable oils.

Abstract: A process and apparatus for producing a synthesis gas for use as a gaseous fuel or as feed into a Fischer-Tropsch reactor to produce a liquid fuel in a substantially self-sustaining process. A slurry of particles of carbonaceous material in water, and hydrogen from an internal source, are fed into a hydro-gasification reactor under conditions whereby methane rich producer gases are generated and fed into a steam pyrolytic reformer under conditions whereby synthesis gas comprising hydrogen and carbon monoxide are generated. A portion of the hydrogen generated by the steam pyrolytic reformer is fed through a hydrogen purification filter into the hydro-gasification reactor, the hydrogen therefrom constituting the hydrogen from an internal source. The remaining synthesis gas generated by the steam pyrolytic reformer is either used as fuel for a gaseous fueled engine to produce electricity and/or process heat or is fed into a Fischer-Tropsch reactor under conditions whereby a liquid fuel is produced.

Abstract: An embodiment of a ultra low-power data retention latch circuit involves a slave latch SL that concurrently latches the same data that is loaded into a main circuit (such as a main latch ML) during normal operation. When the circuit enters a low power (data retention) mode, power (VCC) to the main latch ML is removed and the slave latch SL retains the most recent data (retained data SA, SA-). When power is being restored to the main latch ML, the slave latch's retained data SA, SA- is quickly restored to the main latch ML through what constitute Set and Reset inputs SAR, SAR- of the ML. This arrangement ensures that data restoration is much quicker than conventional arrangements that require the output data path DATA- to be stabilized before power is re-applied to the main latch. Further, there is no need to wait for power to the ML to be stable before restoring data from the SL to the ML, providing an increase in data restoration speed over conventional data retention latches.