Patents by Inventor An Tran

An Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050239244
    Abstract: The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.
    Type: Application
    Filed: April 21, 2005
    Publication date: October 27, 2005
    Inventors: Luan Tran, Fred Fishburn
  • Publication number: 20050236656
    Abstract: The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.
    Type: Application
    Filed: April 26, 2004
    Publication date: October 27, 2005
    Inventors: Luan Tran, Fred Fishburn
  • Publication number: 20050236649
    Abstract: The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.
    Type: Application
    Filed: April 21, 2005
    Publication date: October 27, 2005
    Inventors: Luan Tran, Fred Fishburn
  • Publication number: 20050239243
    Abstract: The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.
    Type: Application
    Filed: April 21, 2005
    Publication date: October 27, 2005
    Inventors: Luan Tran, Fred Fishburn
  • Publication number: 20050236429
    Abstract: A concentrated flavour dispensing machine having displacement pumps for delivering between a few millilitres and few ounces of fluids having a viscosity value between 1 to 4000 centepoise is described. The dispensing machine includes a cabinet for containing a multitude of displacement pumps, where each displacement pump is in direct fluid communication with a respective storage tank, and a control panel having a programmable microprocessor mounted to the cabinet for receiving user selections and controlling each individual pump. Each displacement pump includes a stepper motor in engagement with a threaded drive rod for advancing a piston by any one of several predetermined distances to dispense a corresponding volume of fluid. The control panel receives a valid user selection for actuating one or more pumps to dispense the appropriate volume of a concentrated flavouring fluid.
    Type: Application
    Filed: April 23, 2004
    Publication date: October 27, 2005
    Inventors: Michael Duck, Garth Illsley, Charles Jollymore, Ian MacLean, Kevin Stoneman, Dzung Tran, Avery Wilson, Kim Kanigan
  • Publication number: 20050237795
    Abstract: A method of performing a thermally assisted write operation on a selected two conductor spin valve memory (SVM) cell having a material wherein the coercivity is decreased upon an increase in temperature. In a particular embodiment, a first write magnetic field is established by a first write current flowing from a first voltage potential to a second voltage potential as applied to the first conductor. A second write magnetic field is established by a second write current flowing from a third voltage potential to a fourth voltage potential as applied to the second conductor. The voltage potential of the first conductor is greater than the voltage potential of the second conductor. As a result, a third current, flows from the first conductor through the SVM cell to the second conductor. The SVM cell has an internal resistance such that the flowing current generates heat within the SVM cell. As the SVM cell is self heated, the coercivity of the SVM cell falls below the combined write magnetic fields.
    Type: Application
    Filed: April 26, 2004
    Publication date: October 27, 2005
    Inventors: Frederick Perner, Thomas Anthony, Robert Walmsley, Lung Tran
  • Patent number: 6957920
    Abstract: A ferrule assembly having highly protruding optical fibers and a corresponding method of efficiently, precisely and repeatedly fabricating the ferrule assemblies are provided. In this regard, a ferrule assembly is provided that includes a plurality of optical fibers extending at least about 3.5 ?m beyond the front face. The end portions of the optical fibers of the ferrule assembly may also be substantially coplanar with the end portions of the optical fibers differing in position from one another by no more than 100 nm. The ferrule assembly may be efficiently fabricated by polishing the optical fibers to a desired protrusion without first grinding or polishing the optical fibers to be flush with the front face of the ferrule. The ferrule assembly may be even more efficiently fabricated in instances in which the ferrule includes at least one polishing feature, such as an outwardly extending pedestal or a recessed portion.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: October 25, 2005
    Assignee: Corning Cable Systems LLC
    Inventors: James P. Luther, Dennis M. Knecht, Hieu V. Tran, Robert B. Elkins, II
  • Patent number: 6959134
    Abstract: Optical components may be precisely positioned in three dimensions with respect to one another. A bonder which has the ability to precisely position the components in two dimensions can be utilized. The components may be equipped with contacts at different heights so that as the components come together in a third dimension, their relative positions can be sensed. This information may be fed back to the bonder to control the precise alignment in the third dimension.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: October 25, 2005
    Assignee: Intel Corporation
    Inventors: Ut Tran, Hamid Eslampour
  • Publication number: 20050231855
    Abstract: Systems and methods are disclosed to process a semiconductor substrate by fabricating a first layer on the substrate using semiconductor fabrication techniques; fabricating a second layer above the first layer having one or more NANO-bonding areas; self-assemblying one or more NANO-elements; and bonding the NANO-elements to the NANO-bonding areas.
    Type: Application
    Filed: February 23, 2005
    Publication date: October 20, 2005
    Inventor: Bao Tran
  • Publication number: 20050230822
    Abstract: Systems and methods are disclosed to dissipate heat from a semiconductor substrate. A package for integrated circuit includes a chip having a plurality of chip pads adapted to receive the variety of signals from or to output the same to an external circuit; a lead frame having a plurality of contact points each corresponding to a chip pad; and nano ceramic material in thermal communication with the chip for removing heat from the chip.
    Type: Application
    Filed: February 23, 2005
    Publication date: October 20, 2005
    Inventor: Bao Tran
  • Publication number: 20050229328
    Abstract: Systems and methods for fabricating a wash durable material includes forming a substrate having strands with void spaces in the strands and between the strands; filling at least a part of the void spaces with nano-particles; and forming projections on the substrate.
    Type: Application
    Filed: February 23, 2005
    Publication date: October 20, 2005
    Inventor: Bao Tran
  • Patent number: 6956398
    Abstract: The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: October 18, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Hugh Mair, Luan A. Dang, Xiaowei Deng, George B. Jamison, Tam M. Tran, Shyh-Horng Yang, David B. Scott
  • Patent number: 6956779
    Abstract: A digital multibit non-volatile memory integrated system includes autozero multistage sensing. One stage may provide local sensing with autozero. Another stage may provide global sensing with autozero. A twisted bitline may be used for array arrangement. Segment reference may be used for each segment. The system may read data cells using a current sensing one or two step binary search. The system may use inverse voltage mode or inverse current mode sensing. The system may use no current multilevel sensing. The system may use memory cell replica sensing. The system may use dynamic sensing. The system may use built-in byte redundancy. Sense amplifiers capable of sub-volt (<<1V) sensing are described.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: October 18, 2005
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Hieu Van Tran
  • Patent number: 6957252
    Abstract: A method, system, and apparatus for synchronizing device, node, and drawer addresses between two networks within a data processing system is provided. In one embodiment, a service processor assigns a plurality of SPCN addresses to each of a plurality of devices in the data processing system. System firmware then determines the RIO addresses corresponding to the plurality of devices. If one of the SPCN addresses is not the same as the RIO address for the corresponding device, node, or drawer, then the service processor reassigns a new SPCN address to the corresponding device, node, or drawer such that the new SPCN address is identical to the RIO address for a corresponding device, node, or drawer.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: October 18, 2005
    Assignee: International Business Machines Corporation
    Inventors: Tam D. Bui, Chetan Mehta, Keng-Hiup Ng, Jayeshkumar M. Patel, Amir Simon, Kiet Anh Tran
  • Patent number: 6955853
    Abstract: A low density organic polymer impregnated preformed fibrous ceramic article includes a plurality of layers. A front layer includes ceramic fibers or carbon fibers or combinations of ceramic fibers and carbon fibers, and is impregnated with an effective amount of at least one organic polymer. A middle layer includes polymer impregnated ceramic fibers. A back layer includes ceramic fibers or carbon fibers or combinations of ceramic fibers and carbon fibers, and is impregnated with an effective amount of at least one low temperature pyrolyzing organic polymer capable of decomposing without depositing residues.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: October 18, 2005
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Huy K. Tran, Daniel J. Rasky, Christine E. Szalai, Joseph A. Carroll, Ming-ta S. Hsu
  • Publication number: 20050224973
    Abstract: A method and structure for coupling a semiconductor substrate (e.g., a semiconductor chip) to an organic substrate (e.g., a chip carrier). The coupling interfaces a solder member (e.g., a solder ball) to both a conductive pad on the semiconductor substrate and a conductive pad on the organic substrate. Thermal strains on the solder member during thermal cycling may be reduced by having a surface area of the pad on the semiconductor substrate exceed a surface area of the pad on the organic substrate. Thermal strains on the solder member during thermal cycling may also be reduced by having a distance from a centerline of the solder member to a closest lateral edge of the semiconductor substrate exceed about 0.25 mm.
    Type: Application
    Filed: June 8, 2005
    Publication date: October 13, 2005
    Inventors: William Bernier, Charles Carey, Eberhard Gramatzki, Thomas Homa, Eric Johnson, Pierre Langevin, Irving Memis, Son Tran, Robert White
  • Publication number: 20050228780
    Abstract: A method and apparatus for generating search results including searching by subdomain and providing sponsored results by subdomain is provided. A search system according to embodiments of the present invention analyzes search queries to determine if they are to be routed to subdomains and presents results include sponsored hits sponsored on a subdomain by subdomain basis.
    Type: Application
    Filed: April 5, 2004
    Publication date: October 13, 2005
    Applicant: Yahoo! Inc.
    Inventors: Ali Diab, Scott Gatz, Shyam Kapur, David Ku, Chuck Kung, Phu Hoang, Qi Lu, Lynne Pogue, Yuan Shen, Norman Shi, Thai Tran, Eckart Walther, Jeff Weiner
  • Publication number: 20050225418
    Abstract: An electromagnetic coil assembly is provided. The electromagnetic coil assembly includes a bobbin, a coil of magnet wire and a cover piece. The bobbin includes a hub, a first flange and a second flange. The hub has a longitudinal axis. The first and second flanges are spaced axially from each other. The hub and flanges together define a circumferential bobbin channel. The bobbin is made from a material that is an electrical insulator. The coil of magnet wire is positioned around the hub in the circumferential bobbin channel. The magnet wire has first and second ends. The cover piece is self-supporting and is sized to extend circumferentially around the coil of magnet wire. The cover piece is resilient and exerts a compressive force radially inwardly on the coil of magnet wire.
    Type: Application
    Filed: April 8, 2005
    Publication date: October 13, 2005
    Inventors: Truc Tran-Ngoc, Christopher Bennett
  • Publication number: 20050227227
    Abstract: Sequences of nucleic acid oligonucleotides for amplifying different portions of gag and pol genes of HIV-1 and for detecting such amplified nucleic acid sequences are disclosed. Methods of amplifying and detecting HIV-1 nucleic acid in a biological sample using the amplification oligonucleotides specific for gag and pol target sequences are disclosed.
    Type: Application
    Filed: June 3, 2005
    Publication date: October 13, 2005
    Inventors: Yeasing Yang, Steven Brentano, Odile Babola, Nathalie Tran, Guy Vernet
  • Publication number: 20050227273
    Abstract: Various embodiments of the invention provide human protein modification and maintenance molecules (PMMM) and polynucleotides which identify and encode PMMM. Embodiments of the invention also provide expression vectors, host cells, antibodies, agonists, and antagonists. Other embodiments provide methods for diagnosing, treating, or preventing disorders associated with aberrant expression of PMMM.
    Type: Application
    Filed: April 4, 2005
    Publication date: October 13, 2005
    Inventors: Anita Swarnakar, Uyen Tran