Abstract: A speed change device for shifting the gear of a transmission. The transmission includes a first shifter shaft, a first shifter element associated to the first shifter shaft and arranged for movement in an axial direction of the first shifter shaft for actuating a first set of gears. It further comprises a second shifter shaft and a second shifter element associated to the second shifter shaft and arranged for movement in an axial direction of the second shifter shaft for actuating a second set of gears. One of said first and second shifter shafts is hollow and the other of said first and second shifter shafts is partly arranged coaxially inside the hollow shaft.

Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a first amorphous switching structure disposed over a first electrode. A buffer structure is disposed over the first amorphous switching structure. A second amorphous switching structure is disposed over the buffer structure. A second electrode is disposed over the second amorphous switching structure, where the first and second amorphous switching structures are configured to switch between low resistance states and high resistance states depending on whether a voltage from the first electrode to the second electrode exceeds a threshold voltage.

Abstract: Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.

Abstract: An integrated circuit (IC) comprises a regulator circuit, a bootstrap control circuit, and a gate driver that drives a transistor pair in buck or boost mode to switch current through an inductor. The IC has a VIN terminal coupled to receive a voltage generated from an AC power source, a STR terminal coupled to receive a voltage from a stored power source (e.g., a capacitor bank), and a HSB terminal that is capacitively coupled to the inductor. When bucking or boosting, the regulator circuit generates VDD supply voltage from the stored power source, supplies the VDD supply voltage onto the bootstrap control circuit, and the bootstrap control circuit generates a gate driver supply voltage that is supplied to the gate driver circuit. When not bucking or boosting, voltage on the HSB terminal is maintained between a voltage threshold from the AC power source without draining the stored power source.

Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks. Systems and methods are utilized for compensating for leakage and offset in the input blocks and output blocks the in analog neural memory systems.

Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks.

Abstract: In various embodiments chimeric moieties (constructs) are provided that show significant efficacy against cancers. In certain embodiments the constructs comprise a targeting moiety that specifically binds CSPG4 attached to an interferon or to a mutant interferon. In certain embodiments, the constructs comprise anti-CSPG4 antibody attached to an interferon alpha (IFN-?) or to a mutant interferon alpha or to an interferon beta (IFN-?) or to a nutant interferon beta, or to an interferon gamma (IFN-?) or to a mutant interferon gamma.

Abstract: An integrated circuit includes a gate driver circuit that controls high side and low side transistors to operate in buck or boost mode. In buck operating mode, after switching off the low side transistor, the gate driver circuit controls the high side transistor in a constant current mode. After the low side transistor is disabled and no longer conducts current, then the gate driver circuit controls the high side transistor to operate in full-enhancement mode. In boost operating mode, after switching off the high side transistor, the gate driver circuit controls the low side transistor in a constant current mode. After the high side transistor is disabled, then the gate driver circuit controls the low side switching transistor to operate in full-enhancement mode. In both buck and boost operation, the gate driver circuit operates without dead time in which both the high side and low side transistors are off.

Abstract: A system and method for controlling gas turbine engines with maximum thrust of less than 500 kgf. The control system includes electronic control unit (“ECU”), sensors and actuators. To ensure the requirement of compactness, physical control system simplicity but maintain stability and accurate operation for the engine, the control system does not include components such as Fuel Control Unit (“FCU”), alternator and corresponding rectifier circuits. A sensor, instead of alternator's wave form signal, is used to detect the rotational speed of the engine. Voltage regulation into the electric motor driving the fuel pump controls fuel flow, instead of the FCU. The control method consists of upper and lower limits computation calculation blocks of the control signal, and PID control algorithm block with coefficients designed to be suitable for the engine operating ranges. Control is implemented through a 7-step calculation process. Piecewise linearization modeling and tuning PID coefficients is also presented.

Abstract: Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.

Abstract: The present disclosure relates to an integrated circuit (IC) comprising an adhesion layer to enhance adhesion of an electrode. In some embodiments, the IC comprises a via dielectric layer, an adhesion layer, and a first electrode. The adhesion layer overlies the via dielectric layer, and the first electrode overlies and directly contacts the adhesion layer. The adhesion layer has a first surface energy at an interface at which the first electrode contacts the adhesion layer, and the first electrode has a second surface energy at the interface. Further, the first surface energy is greater than the second surface energy to promote adhesion. The present disclosure also relates to a method for forming the IC.

Abstract: A remote speaker microphone (RSM) unit enables a user to use either a headset or an in-ear speaker with the RSM unit. The RSM unit includes a first RSM connection for communicating and connectable with the first connection of the headset; and a second RSM connection for communicating and connectable with the second connection of the in-ear speaker. Connecting either the headset or the in-ear speaker to the RSM unit disables the speaker and microphone of the RSM unit. At least one of the first and second connections are wireless, e.g., Bluetooth or NFC, and at least one of the first and second RSM connections are wireless connections communicable with the first and second connections, respectively. In addition or the alternative, at least one of said first connection and said second connection are electrical plugs and at least one of said first and second RSM connections are corresponding electrical jacks.

Abstract: Fusion Protein compositions comprising masked IFNs and methods of making masked IFNs are disclosed herein. Consequently, the masked IFNs can be fused to a Mab or binding fragment thereof and be administered to patients as a therapeutic modality and provide a method of treating cancer, immunological disorders and other disease.

Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.

Abstract: Disclosed prosthetic valves can comprise a sewing ring configured to secure the valve to an implantation site. Some disclosed valves comprise a resiliently collapsible frame having a neutral configuration and a collapsed deployment configuration. Some disclosed frames can self-expand to the neutral configuration when released from the collapsed deployment configuration. Collapsing a disclosed valve can provide convenient access to the sewing ring, such as for securing the valve to the implantation site, as well as for the insertion of the valve through relatively small surgical incisions.

Abstract: A kit for discharging electrons from a human comprises at least two electrically conductive electrodes. The electrodes are adapted for creating an electrical connection with skin of the human. There is an electrically conductive pad with electrically conductive pad wires, one for each electrode for connection to the respective electrode to the pad. Electrically conductive grounding wire is provided for electrically grounding the pad. The kit can comprise electrically conductive gel for use with the electrodes to enhance electrically conductivity. The kit is designed, when assembled and used to treat a human, for withdrawing excess electrons from the human for improved health.

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure has a plurality of sub-layers including one or more metals having non-zero concentrations that change as a distance from the first electrode increases.