Patents by Inventor An Tsai

An Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200098802
    Abstract: A device includes a substrate, a light sensitive element, a pinning region, a lightly-doped region, a floating node, and a gate stack. The light sensitive element is in the substrate. The pinning region is in the substrate and is over the light sensitive element. The lightly-doped region is in the pinning region. The floating node is in the pinning region. The floating node is spaced from and is surrounded by the lightly-doped region. A first portion of the pinning region between the floating node and the lightly-doped region forms a channel region. A gate stack is over the channel region.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 26, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Bo-Tsung TSAI
  • Publication number: 20200098799
    Abstract: Some embodiments relate to a device array including a plurality of devices arranged in a semiconductor substrate. A protection ring circumscribes an outer perimeter of the device array. The protection ring includes a first ring neighboring the device array, a second ring circumscribing the first ring and meeting the first ring at a first p-n junction, and a third ring circumscribing the second ring and meeting the second ring at a second p-n junction. The first ring has a first width, the second ring has a second width, and the third ring has a third width. At least two of the first width, the second width, and the third width are different from one another.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Tsung-Han Tsai, Chun-Hao Chou, Kuo-Cheng Lee, Yung-Lung Hsu, Yun-Wei Cheng
  • Publication number: 20200094298
    Abstract: A method includes introducing ozone toward a photoresist layer over a substrate. The ozone is decomposed into dioxygen and first atomic oxygen. The dioxygen is decomposed into second atomic oxygen. The first atomic oxygen and the second atomic oxygen are reacted with the photoresist layer. An apparatus that performs the method is also disclosed.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 26, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Chuan CHANG, Shao-Yen KU, Wen-Chang TSAI, Shang-Yuan YU, Chien-Wen HSIAO, Fan-Yi HSU
  • Publication number: 20200098896
    Abstract: A semiconductor device includes a substrate, a first fin extending from the substrate, a first gate structure over the substrate and engaging the first fin, and a first epitaxial feature partially embedded in the first fin and raised above a top surface of the first fin. The semiconductor device further includes a second fin extending from the substrate, a second gate structure over the substrate and engaging the second fin, and a second epitaxial feature partially embedded in the second fin and raised above a top surface of the second fin. A first depth of the first epitaxial feature embedded into the first fin is smaller than a second depth of the second epitaxial feature embedded into the second fin.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Fu-Tsun Tsai, Tong Jun Huang, I-Chih Chen, Chi-Cherng Jeng
  • Publication number: 20200098605
    Abstract: An apparatus includes: a first image capture module, a second image capture module, and a first projector. The first image capture module has a first optical axis forming an angle from approximately 70° to approximately 87° with respect to the surface of a carrier. The second image capture module has a first optical axis forming an angle of approximately 90° with respect to the surface of the carrier. The first projector has a first optical axis forming an angle from approximately 40° to approximately 85° with respect to the surface of the carrier.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 26, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun Hung TSAI, Hsuan Yu CHEN, Ian HU, Meng-Kai SHIH, Shin-Luh TARNG
  • Publication number: 20200100361
    Abstract: A flexible assembly for a display device and the display device are provided. The flexible assembly includes a flexible substrate, and a first output pad, a second output pad, a third output pad and a fourth output pad that are arranged on the substrate. The first output pad, the second output pad, the third output pad and the fourth output pad are sequentially arranged along a first direction and are spaced apart from each other. A pitch is between each output pad and an adjacent output pad, and the pitch is a sum of a spacing distance between each output pad and the adjacent output pad and a width of the adjacent output pad in the first direction. The pitch between the first output pad and the adjacent second output pad is smaller than the pitch between the third output pad and the adjacent fourth output pad.
    Type: Application
    Filed: March 27, 2019
    Publication date: March 26, 2020
    Inventors: Liqiang Chen, Paoming Tsai, Weifeng Zhou, Chen Xu, Jifeng Tan
  • Publication number: 20200098618
    Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) substrate without bond interface voids and/or without delamination between layers. In some embodiments, a first high ? bonding structure is formed over a handle substrate. A device layer is formed over a sacrificial substrate. Outer most sidewalls of the device layer are between outer most sidewalls of the sacrificial substrate. A second high ? bonding structure is formed over the device layer. The first high ? bonding structure is bonded to the second high ? bonding structure, such that the device layer is between the sacrificial substrate and the handle substrate. A first removal process is performed to remove the sacrificial substrate. The first removal process comprises performing a first etch into the sacrificial substrate until the device layer is reached.
    Type: Application
    Filed: December 20, 2018
    Publication date: March 26, 2020
    Inventors: Min-Ying Tsai, Yeur-Luen Tu
  • Publication number: 20200095394
    Abstract: A method for manufacturing terephthalic acid includes the following operations: providing a raw material, in which the raw material includes a first raw material including polyethylene terephthalate; performing a depolymerization reaction on the first raw material to form a depolymerization product, in which the depolymerization product includes disodium terephthalate; performing a decolorization process on the disodium terephthalate to form decolorized disodium terephthalate and precipitated sludge; separating the decolorized disodium terephthalate and the sludge; and forming terephthalic acid from the decolorized disodium terephthalate after separating the decolorized disodium terephthalate and the sludge.
    Type: Application
    Filed: January 23, 2019
    Publication date: March 26, 2020
    Inventors: Po-Chen LAI, Jyun-Sian LEE, Sih-Hao CHIANG, Chin-Shui LIANG, Hsiang-Chin TSAI
  • Publication number: 20200096743
    Abstract: An optical image capturing system includes, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. The first, the second and the third lens elements all have refractive power. The fourth lens element with refractive power has both surfaces being aspheric. The fifth lens element with refractive power has both surfaces being aspheric. The sixth lens element with refractive power has an image-side surface having at least one convex shape at a peripheral region thereof and both surfaces being aspheric. The seventh lens element with refractive power has an image-side surface having at least one convex shape at a peripheral region thereof, wherein both surfaces being aspheric, and at least one surface has at least one inflection point thereon.
    Type: Application
    Filed: November 28, 2019
    Publication date: March 26, 2020
    Inventors: Tsung-Han TSAI, Hsin-Hsuan HUANG
  • Publication number: 20200097100
    Abstract: An input device includes a wheel supporting structure, a scroll wheel, a hook part, a linking part, and a switching mechanism. The scroll wheel is rotatably supported by the wheel supporting structure, is exposed from the input device, and has a rotary shaft with a plurality of toothed slots thereon. The hook part is disposed biased on the wheel supporting structure to selectively engage with the toothed slots. The linking part is pivotally connected to the wheel supporting structure. The switching mechanism includes an abutting part and a switching part. The abutting part abuts against the linking part. The switching part is coupled to the abutting part. Therein, the switching mechanism is operable to move the abutting part through the switching part to rotate the linking part to abut against and move the hook part to disengage from the toothed slots.
    Type: Application
    Filed: August 15, 2019
    Publication date: March 26, 2020
    Inventors: Ching-Chin Chang, Wen-Yu Tsai, Feng-Wei Su, Chun-Chieh Chen
  • Publication number: 20200095119
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip including an epitaxial layer overlying a microelectromechanical systems (MEMS) substrate. The method includes bonding a MEMS substrate to a carrier substrate, the MEMS substrate includes monocrystalline silicon. An epitaxial layer is formed over the MEMS substrate, the epitaxial layer has a higher doping concentration than the MEMS substrate. A plurality of contacts are formed over the epitaxial layer, the plurality of contacts respectively form ohmic contacts with the epitaxial layer.
    Type: Application
    Filed: July 18, 2019
    Publication date: March 26, 2020
    Inventors: Kuei-Sung Chang, Chia-Hua Chu, Shang-Ying Tsai
  • Publication number: 20200097847
    Abstract: Techniques are disclosed for facilitating the tuning of hyperparameter values during the development of machine learning (ML) models using visual analytics in a data science platform. In an example embodiment, a computer-implemented data science platform is configured to generate, and display to a user, interactive visualizations that dynamically change in response to user interaction. Using the introduced technique, a user can, for example, 1) tune hyperparameters through an iterative process using visual analytics to gain and use insights into how certain hyperparameters affect model performance and convergence, 2) leverage automation and recommendations along this process to optimize the tuning given available resources, 3) collaborate with peers, and 4) view costs associated with executing experiments during the tuning process.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 26, 2020
    Inventors: Gregorio Convertino, Tianyi Li, Haley Allen Most, Wenbo Wenbo, Yi-Hsun Tsai, Michael Tristan Zajonc, Michael John Lee Williams
  • Publication number: 20200097631
    Abstract: A method for forming a photomask is provided. The method includes: receiving an initial layout including a plurality of first patterns and a plurality of second patterns; decomposing the initial layout into a first layout including the plurality of first patterns and a second layout including the plurality of second patterns; inserting a plurality of third patterns into the first layout, wherein each of the plurality of third patterns is adjacent to at least one of the plurality of first patterns; comparing the first layout and the second layout; identifying a fourth pattern as an overlapping portion of the plurality of third patterns overlapping one of the plurality of second patterns; increasing a width of the fourth pattern; and outputting the first layout including the first patterns, the third patterns and the fourth patterns into a first photomask.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: CHIN-MIN HUANG, CHING-HUNG LAI, JIA-GUEI JOU, YIN-CHUAN CHEN, CHI-MING TSAI
  • Publication number: 20200098407
    Abstract: A spin-orbit-torque (SOT) magnetic device includes a bottom metal layer, a first magnetic layer disposed over the bottom metal layer, a spacer layer disposed over the first magnetic layer, and a second magnetic layer disposed over the spacer layer. A diffusion barrier layer for suppressing metal elements of the first magnetic layer from diffusing into the bottom metal layer is disposed between the bottom metal layer and the first magnetic layer.
    Type: Application
    Filed: May 30, 2019
    Publication date: March 26, 2020
    Inventors: Wilman TSAI, Shy-Jay LIN, Mingyuan SONG
  • Publication number: 20200093829
    Abstract: Provided is a composition for wound healing, which includes adenine and a pharmaceutically acceptable salt thereof. Also provided is a method for enhancing wound healing in a subject in need thereof including administering to the subject the composition.
    Type: Application
    Filed: November 27, 2019
    Publication date: March 26, 2020
    Inventors: Han-Min Chen, Cheng-Yi Kuo, Chun-Fang Huang, Jiun-Tsai Lin
  • Publication number: 20200099368
    Abstract: An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.
    Type: Application
    Filed: August 9, 2019
    Publication date: March 26, 2020
    Inventors: Shao-Yu Steve Wang, Chien-Te Wu, Shang-Chih Hsieh, Nick Tsai
  • Publication number: 20200098982
    Abstract: Some embodiments relate to a method for manufacturing a memory device. The method includes forming a first masking layer disposed over a dielectric layer, the first masking layer exhibiting sidewalls defining an opening disposed above a magnetoresistive random-access memory (MRAM) cell located in an embedded memory region. A first etch is performed to form a first via opening within the dielectric layer above the MRAM cell. A top electrode via layer formed over the MRAM cell and the dielectric layer. A first planarization process performed on the top electrode via layer to remove part of the top electrode via layer and define a top electrode via having a substantially flat top surface.
    Type: Application
    Filed: May 10, 2019
    Publication date: March 26, 2020
    Inventors: Harry-Hak-Lay Chuang, Chen-Pin Hsu, Hung Cho Wang, Wen-Chun You, Sheng-Chang Chen, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
  • Publication number: 20200098616
    Abstract: Examples of a technique for forming a dielectric material for an integrated circuit are provided herein. In an example, an integrated circuit workpiece is received that includes a recess. A first dielectric precursor is deposited in the recess. The first dielectric precursor includes a non-semiconductor component. A second dielectric precursor is deposited in the recess on the first dielectric precursor, and an annealing process is performed such that a portion of the non-semiconductor component of the first dielectric precursor diffuses into the second dielectric precursor. The non-semiconductor component may include oxygen, and the annealing process may be performed in one of a vacuum or an inert gas environment.
    Type: Application
    Filed: March 25, 2019
    Publication date: March 26, 2020
    Inventors: Chih-Tang Peng, Shuen-Shin Liang, Keng-Chu Lin, Teng-Chun Tsai
  • Publication number: 20200098889
    Abstract: Some embodiments of the present disclosure relate to a HEMT. The HEMT includes a heterojunction structure having a second III/V semiconductor layer arranged over a first III/V semiconductor layer. Source and drain regions are arranged over the substrate and spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. A first passivation layer is disposed about sidewalls of the gate structure and extending over an upper surface of the gate structure, wherein the first passivation layer is made of a III-V material. A second passivation layer overlies the first passivation layer and made of a material composition different from a material composition of the first passivation layer. The second passivation layer has a thickness greater than that of the first passivation layer.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • Publication number: 20200095397
    Abstract: An additive composition comprises one or more calcium cis-1,2-cyclohexanedicarboxylate salts. The calcium 1,2-cyclohexanedicarboxylate salts have a BET specific surface area of 20 m2/g or more. A method for producing a thermoplastic polymer composition entails mixing the additive composition with a thermoplastic polymer, melting the resulting admixture, and letting the admixture solidify to produce a polymer composition.
    Type: Application
    Filed: September 26, 2019
    Publication date: March 26, 2020
    Inventors: Xiaoyou Xu, Chi-Chun Tsai, Xinfei Yu, Darin L. Dotson, Keith A. Keller, Michael J. Mannion, Daniel T. McBride