Patents by Inventor An Wei Wei

An Wei Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6972239
    Abstract: A method of fabricating a PCMO thin film at low temperature for use in a RRAM device includes preparing a PCMO precursor; preparing a substrate; placing the substrate into a MOCVD chamber; introducing the PCMO precursor into the MOCVD chamber to deposit a PCMO thin film on the substrate; maintaining a MOCVD vaporizer at between about 240° C. to 280° C. and maintaining the MOCVD chamber at a temperature of between about 300° C. to 400° C.; removing the PCMO thin-film bearing substrate from the MOCVD chamber; and completing the RRAM device.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: December 6, 2005
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Tingkai Li, Wei-Wei Zhuang, Lawrence J. Charneski, David R. Evans, Sheng Teng Hsu
  • Patent number: 6972211
    Abstract: Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: December 6, 2005
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Sheng Teng Hsu, Wei Pan, Wei-Wei Zhuang
  • Publication number: 20050266686
    Abstract: A method of fabricating a CMR thin film for use in a semiconductor device includes preparing a CMR precursor in the form of a metal acetate based acetic acid solution; preparing a wafer; placing a wafer in a spin-coating chamber; spin-coating and heating the wafer according to the following: injecting the CMR precursor into a spin-coating chamber and onto the surface of the wafer in the spin-coating chamber; accelerating the wafer to a spin speed of between about 1500 RPM to 3000 RPM for about 30 seconds; baking the wafer at a temperature of about 180° C. for about one minute; ramping the temperature to about 230° C.; baking the wafer for about one minute at the ramped temperature; annealing the wafer at about 500° C. for about five minutes; repeating said spin-coating and heating steps at least three times; post-annealing the wafer at between about 500° C. to 600° C. for between about one to six hours in dry, clean air; and completing the semiconductor device.
    Type: Application
    Filed: May 27, 2004
    Publication date: December 1, 2005
    Inventors: Wei-Wei Zhuang, Tingkai Li, Wei Pan, David Evans, Sheng Hsu
  • Publication number: 20050245039
    Abstract: PrCaMnO (PCMO) thin films with predetermined memory-resistance characteristics and associated formation processes have been provided. In one aspect the method comprises: forming a Pr3+1?xCa2+xMnO thin film composition, where 0.1<x<0.6; in response to the selection of x, varying the ratio of Mn and O ions as follows: O2?(3±20%); Mn3+((1?x)±20%); and, Mn4+(x±20%). When the PCMO thin film has a Pr3+0.70Ca2+0.30Mn3+0.78Mn4+0.22O2?2.96 composition, the ratio of Mn and O ions varies as follows: O2?(2.96); Mn3+((1?x)+8%); and, Mn4+(x?8%). In another aspect, the method creates a density in the PCMO film, responsive to the crystallographic orientation. For example, if the PCMO film has a (110) orientation, a density is created in the range of 5 to 6.76 Mn atoms per 100 ?2 in a plane perpendicular to the (110) orientation.
    Type: Application
    Filed: April 30, 2004
    Publication date: November 3, 2005
    Inventors: Tingkai Li, Wei-Wei Zhuang, David Evans, Sheng Hsu
  • Publication number: 20050239262
    Abstract: A method is provided for forming a Pr0.3Ca0.7MnO3 (PCMO) thin film with crystalline structure-related memory resistance properties. The method comprises: forming a PCMO thin film with a first crystalline structure; and, changing the resistance state of the PCMO film using pulse polarities responsive to the first crystalline structure. In one aspect the first crystalline structure is either amorphous or a weak-crystalline. Then, the resistance state of the PCMO film is changed in response to unipolar pulses. In another aspect, the PCMO thin film has either a polycrystalline structure. Then, the resistance state of the PCMO film changes in response to bipolar pulses.
    Type: Application
    Filed: April 23, 2004
    Publication date: October 27, 2005
    Inventors: Wei-Wei Zhuang, Tingkai Li, Sheng Hsu, Fengyan Zhang
  • Publication number: 20050226888
    Abstract: Provided are methods of generating an immune response to an antigen. The method comprises priming an individual by administering an expression vector encoding the antigen. The vectors comprises a transcription unit encoding a secretable fusion protein, the fusion protein containing an antigen and CD40 ligand. Administration of a fusion protein containing the antigen and CD40 ligand is used to enhance the immune response above that obtained by vector administration alone. The invention methods may be used to generate an immune response against cancer expressing a tumor antigen such as a mucin or human papilloma viral tumor antigen and to generate an immune response against an infectious agent. Also provided is a method for simultaneously producing the expression vector and the fusion protein.
    Type: Application
    Filed: December 10, 2004
    Publication date: October 13, 2005
    Inventors: Albert Deisseroth, Yucheng Tang, Wei-Wei Zhang, Xiang-Ming Fang
  • Patent number: 6951751
    Abstract: A novel tyrosine-inducible tyrosine ammonia lyase enzyme was isolated from the yeast Trichosporon cutaneum. This enzyme has a higher activity for tyrosine than for phenylalanine and is useful for the production of para-hydroxycinnamic acid directly from tyrosine. The gene encoding this enzyme was sequenced using 3? and 5? RACE cloning of the TAL cDNA and the gene was expressed in the yeast Saccharomyces cerevisiae and in the bacterium Escherichia coli.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: October 4, 2005
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Sabine Breinig, Wei Wei Qi, Fateme Sima Sariaslani, Todd M. Vannelli, Zhixiong Xue
  • Publication number: 20050207265
    Abstract: Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.
    Type: Application
    Filed: May 16, 2005
    Publication date: September 22, 2005
    Inventors: Sheng Hsu, Tingkai Li, David Evans, Wei-Wei Zhuang, Wei Pan
  • Publication number: 20050196878
    Abstract: A method for forming a doped PGO ferroelectric thin film, and related doped PGO thin film structures are described. The method comprising: forming either an electrically conductive or electrically insulating substrate; forming a doped PGO film overlying the substrate; annealing; crystallizing; and, forming a single-phase c-axis doped PGO thin film overlying the substrate, having a Curie temperature of greater than 200 degrees C. Forming a doped PGO film overlying the substrate includes depositing a doped precursor in the range between 0.1N and 0.5N, with a molecular formula of Pby?xMxGe3O11, where: M is a doping element; y=4.5 to 6; and, x=0.1 to 1. The element M can be Sn, Ba, Sr, Cd, Ca, Pr, Ho, La, Sb, Zr, or Sm.
    Type: Application
    Filed: January 28, 2005
    Publication date: September 8, 2005
    Inventors: Fengyan Zhang, Wei-Wei Zhuang, Jong-Jan Lee, Sheng Hsu
  • Patent number: 6940113
    Abstract: Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: September 6, 2005
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Sheng Teng Hsu, Wei Pan, Wei-Wei Zhuang
  • Patent number: 6939724
    Abstract: A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 ? to 300 ?, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 ? to 3000 ?, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about ?4V to ?5V, having a pulse width of between about 75 nsec to 1 ?sec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 ?sec.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: September 6, 2005
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Wei-Wei Zhuang, Tingkai Li, David R. Evans, Sheng Teng Hsu, Wei Pan
  • Patent number: 6927120
    Abstract: Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: August 9, 2005
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Sheng Teng Hsu, Tingkal Li, David R. Evans, Wei-Wei Zhuang, Wei Pan
  • Publication number: 20050171961
    Abstract: Techniques and tools are described for creating and using application identifiers that act as “fingerprints” for applications. In one aspect, an identifier generation algorithm is applied to application data and an application identifier is generated. The application data comprises graphical icon data, and can further comprise other data (e.g., executable name, registry data). The identifier generation algorithm can be a hashing algorithm that generates a hash value. The application identifier can be sent in a database query, and a database can return results indicating, for example, whether metadata can be obtained from a metadata service, or whether the software application is of a particular type (e.g., a gaming-related application). Application identifiers can be stored, for example, in a data file along with one or more other application identifiers for other software applications. Described techniques and tools can be used in a graphical user interface-based gaming activity center.
    Type: Application
    Filed: January 30, 2004
    Publication date: August 4, 2005
    Inventors: Aaron Culbreth, Roderick Toll, James Hall, Thomas Springer, Wei Wei Ada Cho, C. Evans
  • Patent number: 6921671
    Abstract: A method of fabricating a ferroelectric thin film on an iridium-composite electrode in an integrated circuit device includes preparing a substrate; depositing an iridium-composite bottom electrode on the substrate; annealing the bottom electrode in a first annealing step; depositing a buffer layer on the bottom electrode, including depositing a layer of material taken from the group of materials consisting of HfO2, ZrO2, TiO2, LaOx, La—Al—O, Ti—Al—O, Hf—Al—O, Zr—Al—O, Hf—Zr—O, Zr—Ti—O, Hf—Ti—O, La—Zr—O, La—Hf—O, and La—Ti—O; annealing the buffer layer in a second annealing step; depositing a layer of Bi4Ti3O12, to a thickness of between about 20 nm to 500 nm, on the buffer layer; annealing the ferroelectric layer in a third annealing step; and completing the integrated circuit device.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: July 26, 2005
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Fengyan Zhang, Wei-Wei Zhuang, Sheng Teng Hsu
  • Publication number: 20050158994
    Abstract: A Pr1-XCaXMnO3 (PCMO) spin-coat deposition method for eliminating voids is provided, along with a void-free PCMO film structure. The method comprises: forming a substrate, including a noble metal, with a surface; forming a feature, such as a via or trench, normal with respect to the substrate surface; spin-coating the substrate with acetic acid; spin-coating the substrate with a first, low concentration of PCMO solution; spin-coating the substrate with a second concentration of PCMO solution, having a greater concentration of PCMO than the first concentration; baking and RTA annealing (repeated one to five times); post-annealing; and, forming a PCMO film with a void-free interface between the PCMO film and the underlying substrate surface. The first concentration of PCMO solution has a PCMO concentration in the range of 0.01 to 0.1 moles (M). The second concentration of PCMO solution has a PCMO concentration in the range of 0.2 to 0.5 M.
    Type: Application
    Filed: January 15, 2004
    Publication date: July 21, 2005
    Inventors: Wei-Wei Zhuang, Lisa Stecker, Gregory Stecker, Sheng Hsu
  • Publication number: 20050141269
    Abstract: Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.
    Type: Application
    Filed: February 24, 2005
    Publication date: June 30, 2005
    Inventors: Sheng Hsu, Wei-Wei Zhuang
  • Patent number: 6911361
    Abstract: A method of applying a PCMO thin film on an iridium substrate for use in a RRAM device, includes preparing a substrate; depositing a barrier layer on the substrate; depositing a layer of iridium on the barrier layer; spin coating a layer of PCMO on the iridium; baking the PCMO and substrate in a three-step baking process; post-bake annealing the substrate and the PCMO in a RTP chamber; repeating said spin coating, baking and annealing steps until the PCMO has a desired thickness; annealing the substrate and PCMO; depositing a top electrode; and completing the RRAM device.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: June 28, 2005
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Fengyan Zhang, Wei-Wei Zhuang, Wei Pan, Sheng Teng Hsu
  • Publication number: 20050136602
    Abstract: A memory array dual-trench isolation structure and a method for forming the same have been provided.
    Type: Application
    Filed: January 19, 2005
    Publication date: June 23, 2005
    Inventors: Sheng Hsu, Wei Pan, Wei-Wei Zhuang
  • Patent number: 6909692
    Abstract: The present invention contemplates an apparatus and a method for limiting the number of specified messages placed onto a network thus to improve network performance. An element management system, upon detecting that a defined threshold has been exceeded for specified types of messages, determines which network element is generating the greatest number of such messages. Thereafter, the element management system instructs the network element that is generating the largest number of alarm messages to cease transmitting a specified type of alarm message. In an alternate embodiment of the invention, if the event flow rate is still too high, the element management system may instruct the cross connect network element to stop sending all threshold types of alarms. Finally, if the event flow rate is still too high, the element management system may cause all QoS alarms from the one network element to not be transmitted.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: June 21, 2005
    Assignee: Alcatel
    Inventors: Sandeep Sharma, Wei Wei, Phillip Heisler
  • Patent number: 6905873
    Abstract: Described are simplified and efficient methods for preparing recombinant adenovirus using liposome-mediated cotransfection and the direct observation of a cytopathic effect (CPE) in the transfected cells. Also disclosed are compositions and methods involving novel p53 adenovirus constructs, including methods for restoring p53 function and tumor suppression in cells and animals having abnormal p53.
    Type: Grant
    Filed: April 2, 1996
    Date of Patent: June 14, 2005
    Assignee: Board of Regents, The University of Texas System
    Inventors: Wei-Wei Zhang, Jack A Roth