Abstract: A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.

Abstract: A gimbal system, a gimbal and a locking device are provided. The locking device is configured to be disposed on the shaft arm. The locking device includes an upper cover, a lower cover, a quick release plate and a locking assembly. The upper cover is disposed on the shaft arm. The lower cover is disposed on the side of the shaft arm opposite to the upper cover, and the upper cover and the lower cover can move together along the first direction. The quick release plate is used to install a load. The quick release plate is disposed on the side of the upper cover away from the lower cover. The quick release plate can move along a second direction on the upper cover. The locking assembly passes through the lower cover and the upper cover. When the locking assembly is tightened, the upper cover and the lower cover are locked and fixed to the shaft arm, and the quick release plate and the upper cover are locked and fixed on the upper cover.

Abstract: The disclosure provides a method of fabricating a semiconductor device, where the method includes the following operations. A semiconductor stack including a silicon-containing layer, an oxide deposited on a portion of the silicon-containing layer, an underlayer, and a resist layer is formed. The resist layer is patterned to form a first opening in the resist layer. The underlayer is etched to extend the first opening into the underlayer, where a top surface of the oxide is exposed by the first opening. The oxide and the underlayer are etched with a first etchant, where a ratio of etching rates of the oxide and the underlayer is about 1:1. The oxide and the silicon-containing layer are etched with a second etchant to form a second opening below the first opening, where an etching rate of the oxide is higher than that of the silicon-containing layer.

Abstract: A solar cell is provided. The solar cell includes: an N-type silicon substrate having a first surface and a second surface, a tunnel passivation structure and a first passivation and anti-reflection film formed on the first surface, a boron-doped emitter structure layer including a first emitter layer and a second emitter region formed on the second surface, a second passivation and anti-reflection film formed on the emitter structure layer, a first electrode configured to be in electrical contact with the second emitter region, and a second electrode configured to be in electrical contact with the tunnel passivation structure. The solar cell of the present application has a selective emitter structure. The metal contact region has a large junction depth to meet the metallization requirements. The region outside the metal contact region has a small junction depth to improve the optical response.

Abstract: Semiconductor structures and methods are provided. A method according to the present disclosure includes forming a first channel member, a second channel member directly over the first channel member, and a third channel member directly over the second channel member, depositing a first metal layer around each of the first channel member, the second channel member, and the third channel member, removing the first metal layer from around the second channel member and the third channel member while the first channel member remains wrapped around by the first metal layer, after the removing of the first metal layer, depositing a second metal layer around the second channel member and the third channel member, removing the second metal layer from around the third channel member, and after the removing of the second metal layer, depositing a third metal layer around the third channel member.

Abstract: A pure electric modular subsea test tree is provided, which includes a connect-disconnect device, wherein the first channel is formed in the connect-disconnect device; the connect-disconnect device is provided with a locking assembly and a connection drive mechanism for driving the locking assembly, and the first electrical connection plug is embedded in the connect-disconnect device, and the connection drive mechanism is electrically connected with the first electrical connection plug; a shear-seal assembly, wherein a second channel communicated with the first channel is formed in the shear-seal assembly; the shear-seal assembly includes at least one shear-seal device capable of plugging the second channel; a connection part is formed on the shear-seal assembly; a heating device is arranged at one end of the shear-seal device far from the connection part. The disclosure relates to a pure electric modular subsea test tree, which has fast response speed and high operation safety.

Abstract: A four times contacted poly pitch (4CPP) static random-access memory (SRAM) cell layout is disclosed that forms six SRAM transistors from one OD region and four poly lines at a frontside of a substrate and provides a double-sided routing structure for word lines, bit lines, and/or voltage lines. For example, a vertical SRAM is disclosed that stacks transistors, vertically, to facilitate scaling needed for advanced IC technology nodes and improve memory performance. The vertical SRAM further includes a double-sided routing structure, which facilitates placement of bit lines, word lines, and voltage lines in a backside metal one (M1) layer and/or a frontside M1 layer to minimize line capacitance and line resistance.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple meta

Abstract: In an example method, a user equipment (UE) device determines an offset length of time associated with transmitting or receiving data over a wireless network. The UE device transmits an indication of the offset length of time to the wireless network. The UE device transmits or receives, during a first time interval, a first portion of data to or from the wireless network though a first wireless link. The UE device transmits or receives, during a second time interval, a second portion of data to or from the wireless network though a second wireless link. An end of first time interval is offset from a beginning of the second time interval by the offset length of time.

Abstract: An LED display device includes a system board, and multiple daughterboards that are assembled on the system board. The system board includes a drive power circuit, a first gate circuit and a second gate circuit. Each daughterboard includes a substrate, multiple LEDs that are disposed on the substrate, multiple first transistor switches that are respectively connected to the LEDs, and at least one second transistor switch that is connected to the LEDs. With respect to each daughterboard, the first transistor switches and the at least one second transistor switch cooperatively control current flows through the LEDs; the first transistor switches are further connected to the drive power circuit to respectively receive multiple drive currents, and are further connected to the first gate circuit to receive a timing signal; and the at least one second transistor switch is further connected to the second gate circuit to receive a timing signal.

Abstract: A semiconductor device includes first and second active areas, a first gate, a first conductive segment, a first via and a first continuous gate. The first and second active areas extend in a first direction. The first gate crosses over the first active area and the second active area. The first gate includes a first gate portion and a second gate portion electrically isolated from each other. The first conductive segment crosses over the first active area and the second active area. The first via is arranged above the first conductive segment. The first active area and the second active area are coupled through the first conductive segment to the first via. The first continuous gate is disposed between the first conductive segment and the first gate, and crossing over the first active area and the second active area.

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.

Abstract: The present disclosure provides a warm water immersion-based hatching method of silkworm eggs, belonging to the technical field of sericulture production. In the present disclosure, a warm water treatment is conducted on silkworm eggs of a bivoltine silkworm variety in production, and a water temperature and an immersion time are optimized to ensure a higher hatching rate. The silkworm eggs are subjected to the warm water immersion at 49° C. to 51° C. for 15 s to 23 s to rapidly hatch the silkworm eggs without diapause.

Abstract: The present invention discloses a rubber composition, a processing method for obtaining the rubber composition, a rubber hose using the rubber composition and a production method thereof. The rubber composition comprises, in parts by weight, 100 parts of a rubber matrix, 1.5-8 parts of a crosslinking agent, 50-200 parts of a reinforcing filler, 10-100 parts of a plasticizer, and also 0.2-8 parts of an auxiliary crosslinking agent, 2-15 parts of a metal oxide, 1-3 parts of a stabilizer and 1-5 parts of polyethylene glycol, wherein, with respect to 100 parts by weight of total amount of said rubber matrix, said rubber matrix comprises a branched polyethylene with a content represented as A, in which 0<A?100 parts, and both an EPM rubber and an EPDM rubber with a total content represented as B, in which 0?B<100 parts. The beneficial effect is that a rubber hose with good mechanical strength can be prepared from the rubber composition provided in the present invention.

Abstract: The present invention discloses a photochromic resin lens with a refractivity of 1.50 and a preparation method thereof. The lens comprises a resin monomer, a photochromic organic material, an initiator, an antioxidant and a photo stabilizer at a weight ratio of 100:0.01-0.1:1-10:0.1-0.9:0.1-0.9. The resin monomer is a mixture of a monofunctional acrylate, a difunctional acrylate and a tetrafunctional acrylate at a weight ratio of 10-80:10-50:10-50. In the present invention, a low-refractivity photochromic resin lens with a refractivity of 1.50 and an Abbe number of 58 is prepared. The lens does not contain toxic materials, is safer and more environmentally friendly to wear and produce, and has high Abbe number, clear imaging, high visible light transmittance, and high product pass rate. The visible light transmittance under UV irradiation is less than 20%, the color is deep, and the photochromic effect is good.