Patents by Inventor AN YI LIN

AN YI LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240140178
    Abstract: The invention discloses a built-in roll cover, includes a layer of leather and a support frame, the layer of leather is connected with the support frame, the support frame includes a large front bar assembly, a side rail assembly and a rear bar assembly, the large front bar assembly is connected to the rear bar assembly through a side rail assembly, the side rail assembly is connected to the side rail of the car through a clamp assembly, the large front bar assembly includes a large front bar and a large front bar plug strip, the large front bar is provided with a large front bar groove, the large front bar plug strip is connected with the layer of leather, the large front bar plug strip is stuck in the large front bar groove, the rear bar assembly is connected to the side rail assembly through the rear bar fixing assembly, the rear bar fixing assembly includes a rear bar joint and a rear bar fixing base, the rear bar fixing base is connected with the side rail assembly, the rear bar joint is engaged with the
    Type: Application
    Filed: March 27, 2023
    Publication date: May 2, 2024
    Inventors: Yi Lin, Lei Lin
  • Publication number: 20240146316
    Abstract: A system performs a method of adaptive voltage scaling. The method includes generating a voltage adjustment signal based on a hint from a frequency-locked loop (FLL). The FLL includes an oscillator that generates a clock signal at a clock frequency. The voltage adjustment signal is sent to a power management unit (PMU) to cause the PMU to supply an adjusted operating voltage to the FLL. The method further includes updating a minimum code set according to the adjusted operating voltage and an operating temperature. The clock frequency of the oscillator is generated to match a target frequency according to the adjusted operating voltage and a code determined by the FLL from the minimum code set.
    Type: Application
    Filed: October 19, 2023
    Publication date: May 2, 2024
    Inventors: Yu-Shu Chen, Hsin-Chen Chen, Kuan Hung Lin, Jeng-Yi Lin
  • Publication number: 20240146176
    Abstract: A method of controlling phase shift pulse width modulation of a power converter, the method includes a step of obtaining sampling signals of an output voltage and current of the power converter. Then, a digital signal processor is used to calculate an output power of the power converter. Next, a comparator is used to compare the output power of the power converter with a reference power. When the output power is less than the reference power, the modulation control of the switch of the power converter enters into hard-switching mode, and when the output power is greater than the reference power, the modulation control of the switch of the power converter enters into soft-switching mode.
    Type: Application
    Filed: November 24, 2022
    Publication date: May 2, 2024
    Inventors: Chun-Chen Chen, Jian-Hsieng Lee, Feng-Yi Lin
  • Publication number: 20240144467
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Publication number: 20240147812
    Abstract: The present application provides an organic light emitting diode (OLED) display panel and a method of manufacturing the same, and a display terminal. The OLED display panel includes an array substrate, a protective layer and a cathode. The array substrate includes a first auxiliary electrode, a second auxiliary electrode, and a third auxiliary electrode. The third auxiliary electrode is connected to the first auxiliary electrode and the second auxiliary electrode. The protective layer is provided with an undercut opening exposing a portion of the third auxiliary electrode. The cathode extends into the undercut opening and is connected to the third auxiliary electrode.
    Type: Application
    Filed: September 26, 2023
    Publication date: May 2, 2024
    Inventors: Huan DUAN, Yi ZHUO, Fangmei LIU, Zhiwei SONG, Gaobo LIN, Kai HU
  • Patent number: 11972139
    Abstract: A read voltage level correction method, a memory storage device, and a memory control circuit unit are provided. The method includes: using a first read voltage level as an initial read voltage level to perform a first data read operation on a first physical unit among multiple physical units to obtain a second read voltage level used to successfully read the first physical unit; recording association information between the first read voltage level and the second read voltage level in a transient look-up table; and performing a second data read operation according to a read level tracking table and the association information recorded in the transient look-up table.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: April 30, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Chun-Wei Tsao, Hsiao-Yi Lin, Wei Lin
  • Patent number: 11974367
    Abstract: A lighting device includes a light board and a light dimmer circuit. The light board includes multiple first light emitting elements and second light emitting elements. The first light emitting elements are disposed in a first area of the light board. The second light emitting elements are disposed in a second area of the light board. The light dimmer circuit is configured to drive the second light emitting elements to generate flickering lights from the second area of the light board, and is configured to drive the first light emitting elements to generate non-flickering lights from the first area of the light board.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: April 30, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Hsien Wang, Ming-Chieh Cheng, Po-Yen Chen, Shih-Chieh Chang, Kuan-Hsien Tu, Xiu-Yi Lin, Ling-Chun Wang
  • Patent number: 11972951
    Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Kao-Feng Lin, Min-Hsiu Hung, Yi-Hsiang Chao, Huang-Yi Huang, Yu-Ting Lin
  • Patent number: 11973958
    Abstract: Methods and apparatus of video coding using sub-block based affine mode are disclosed. According to this method, control-point motion vectors (MVs) associated with the affine mode are determined for a block. A sub-block MV is derived for a target sub-block of the block from the control-point MVs for the block. A prediction offset is determined for a target pixel of the target sub-block using information comprising a pixel MV offset from the sub-block MV for the target pixel according to Prediction Refinement with Optical Flow (PROF). The target pixel of the target sub-block is encoded or decoded using a modified predictor. The modified prediction is generated by clipping the prediction offset to a target range and combining the clipped prediction offset with an original predictor.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: April 30, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Tzu-Der Chuang, Ching-Yeh Chen, Zhi-Yi Lin
  • Patent number: 11973261
    Abstract: An antenna structure with wide radiation bandwidth in a reduced physical space includes a metallic housing, a first feed portion, and a second feed portion. The metallic housing includes a metallic side frame and a metallic back board. The metallic side frame defines a slot, and first and second gaps. The metallic side frame between the first gap and one end of the slot forms a first radiation portion. The second gap divides the first radiation portion into first and second radiation sections. The first feed portion feeds current and signal to the first radiation section, and the first radiation section works in a GPS mode and a WIFI 2.4 GHz mode. The second feed portion feeds current and signal to the second radiation section, and the second radiation section works in a WIFI 5 GHz mode.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: April 30, 2024
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Kun-Lin Sung, Yung-Chin Chen, Yi-Chieh Lee
  • Patent number: 11969288
    Abstract: A three-dimensional ultrasonic imaging method includes transmitting an ultrasonic wave to a fetal head; receiving an ultrasonic echo, obtaining an ultrasonic echo signal, and obtaining the three-dimensional volume data of the fetal head according to the ultrasonic echo signal; according to the characteristics of a median sagittal section of the fetal head, detecting the median sagittal section in the three-dimensional volume data; and displaying the median sagittal section.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: April 30, 2024
    Assignee: Shenzhen Mindray Bio-Medical Electronics Co., Ltd.
    Inventors: Yaoxian Zou, Muqing Lin, Zhijie Chen, Yi Xiong, Bin Yao
  • Publication number: 20240131538
    Abstract: An annular airflow regulating apparatus includes a cup-shaped element and an adjustment element. The cup-shaped element has a bowl and a bottom, integrated to form a first chamber. The bottom has a tapered channel parallel to an axis and penetrating through the bottom. A ring-shaped groove is disposed between the tapered channel and the bottom. The ring-shaped groove has an annular plane perpendicular to the axis. The adjustment element, having a tapered portion and second holes, is movably disposed in the cup-shaped element. The tapered portion protrudes into the tapered channel A tapered annular gap is formed between the tapered portion and the tapered channel. When the adjustment element is moved with respect to the cup-shaped element, a width of the tapered annular gap is varied, and thereupon a flow rate and velocity of the process gas would be varied accordingly.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 25, 2024
    Inventors: CHEN-CHUNG DU, Ming-Jyh Chang, Chang-Yi Chen, Ming-Hau Tsai, Ko-Chieh chao, Yi-Wei Lin
  • Publication number: 20240136227
    Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Ching-Yi Chen, Sheng-Hsuan Lin, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
  • Publication number: 20240133949
    Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 25, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yu-Lin Yang, Chin-Wei Lin, Po-Chao Tsao, Tung-Hsing Lee, Chia-Jung Ni, Chi-Ming Lee, Yi-Ju Ting
  • Publication number: 20240135485
    Abstract: The disclosure relates to tuning configuration parameters for graphics pipeline for better user experience. A device for graphics processing, comprising: hardware engines; a graphics pipeline at least partly implemented by the hardware engines; and a tuner, coupled to the hardware engines and the graphics pipeline, the tuner to: collect statuses of the device during runtime for a previous frame; determine configuration parameters based on the collected statuses, the configuration parameters associated with three-dimensional 3D rendering, pre-processing and video encoding of the graphics pipeline; and tune the graphics pipeline with the determined configuration parameters for processing a next frame.
    Type: Application
    Filed: September 1, 2023
    Publication date: April 25, 2024
    Applicant: Intel Corporation
    Inventors: Fan He, Yi Qian, Ning Luo, Yunbiao Lin, Changliang Wang, Ximin Zhang
  • Patent number: 11968908
    Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Han-Ting Lin, Sin-Yi Yang, Yu-Shu Chen, An-Shen Chang, Qiang Fu, Chen-Jung Wang
  • Patent number: 11965305
    Abstract: An electronic well lid based on electric control travel switch control relates to the technical field of electronic well lids. The electronic well lid based on electric control travel switch control includes a well seat in splined connection with a sliding ring. The sliding ring is provided with a well lid lifting mechanism. A garbage collection mechanism is arranged on the well seat. An arc-shaped groove is formed in the sliding ring. An anti-deviation mechanism is arranged in the arc-shaped groove of the sliding ring. Square grooves are communicated with square holes by way of arrangement of the well lid lifting mechanism and cooperation of first fixing rings and the square grooves. Thus, a drainage speed of the device is increased, pedestrians may continue to pass safely on the well lid in a drainage process of the device, and the protection effect for pedestrians in the drainage process is improved.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: April 23, 2024
    Assignee: JINAN YINGHUA AUTOMATION TECHNOLOGY CO., LTD
    Inventors: Yanchao Li, Yi Yan, Guoyong Lin, Zhi Zhang, Yunbo Li
  • Patent number: 11965069
    Abstract: A heat-shrinkable polyester film made of a polyester-forming resin composition includes a recycled material, and has an exothermic crystallization peak and an endothermic melting peak which are determined via differential scanning calorimetry, and which satisfy relationships of T2?T1?68° C. and T3?T2?78° C., where T1 represents an onset point of the exothermic crystallization peak, T2 represents an end point of the exothermic crystallization peak and an onset point of the endothermic melting peak, and T3 represents an end point of the endothermic melting peak. A method for manufacturing the heat-shrinkable polyester film is also disclosed.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: April 23, 2024
    Assignee: FAR EASTERN NEW CENTURY CORPORATION
    Inventors: Li-Ling Chang, Yow-An Leu, Ting-Yu Lin, Ching-Chun Tsai, Wen-Yi Chang
  • Patent number: 11966587
    Abstract: A method for optimizing a Polar-RNNA quantizer of MLC NAND flash based on deep learning comprises the following steps: Step S1: transforming an MLC flash detection task into a deep learning task, and obtaining three hard-decision read thresholds based on a neural network; Step S2: expanding six soft-decision read thresholds based on the three hard-decision read thresholds; Step S3: constructing an LLR mapping table, and obtaining new LLR information of MLC flash based on the LLR mapping table; Step S4: symmetrizing an MLC flash channel, and performing density evolution; and Step S5: optimizing the soft-decision read thresholds based on a genetic algorithm to obtain an optimal quantization interval. According to the invention, polar codes can be directly used for MLC flash channels without the arduous work of MLC flash channel modeling, so that the reliability of MLC flash is effectively improved.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: April 23, 2024
    Assignee: FUZHOU UNIVERSITY
    Inventors: Pingping Chen, Zhen Mei, Yi Fang, Xu Luo, Zhijian Lin, Feng Chen, Riqing Chen
  • Patent number: 11967504
    Abstract: A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Yi Lee, Jia-Ming Lin, Kun-Yu Lee, Chi On Chui