Patents by Inventor An-Yu CHANG

An-Yu CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240181648
    Abstract: A welding path generating system and a welding path generating method are provided. The welding path generating system includes an image sensor, a storage device, and a processor. The image sensor obtains a sensing image of a welding target. The storage device stores a vision analysis module, an analysis module, and a path planning module. The processor is coupled to the storage device and the image sensor. The processor executes the vision analysis module to analyze the sensing image and create scan data. The processor executes the analysis module to identify weld bead profile information according to the scan data. The processor executes the path planning module to generate welding path information according to the weld bead profile information.
    Type: Application
    Filed: December 6, 2022
    Publication date: June 6, 2024
    Applicant: Metal Industries Research & Development Centre
    Inventors: Ching-Shun Liang, Yu-Zheng Jiang, Cheng-Chang Chiu
  • Publication number: 20240186148
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.
    Type: Application
    Filed: February 9, 2024
    Publication date: June 6, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Hao CHEN, Wei-Han LAI, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20240186414
    Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.
    Type: Application
    Filed: January 2, 2024
    Publication date: June 6, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming LIN, Sai-Hooi YEONG, Ziwei FANG, Bo-Feng YOUNG, Chi On CHUI, Chih-Yu CHANG, Huang-Lin CHAO
  • Publication number: 20240186415
    Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.
    Type: Application
    Filed: February 13, 2024
    Publication date: June 6, 2024
    Inventors: Chih-Yu Ma, Shahaji B. More, Yi-Min Huang, Shih-Chieh Chang
  • Publication number: 20240187722
    Abstract: A measurement assistance system and method are provided. The measurement assistance system includes: a measurement platform, having an operation area configured for a to-be-measured object and a measurement tool to be placed; a camera, arranged on the measurement platform and configured to obtain a measurement image; and a server module, electrically connected to the camera and configured to execute a measurement tool identification program, a measurement part identification program, and a measurement posture identification program according to the measurement image, and determine whether a measurement tool appearance image, a measurement part image, and a measurement posture image are correct. The server module has a processing unit. When the measurement tool appearance image, the measurement part image, and the measurement posture image are all correct, a measurement result is generated according to measurement data.
    Type: Application
    Filed: December 2, 2022
    Publication date: June 6, 2024
    Inventors: CHUN-CHIH KUO, CHIA-HUNG CHANG, BO-YUN HOU, CHENG-YU YANG
  • Patent number: 12003128
    Abstract: An adapter for a charging cradle includes: a perimeter wall defining a channel between first and second ends; a first device interface on an inner surface of the perimeter wall in communication with the first end, the first device interface configured to receive and align a first mobile device configuration with the charging cradle; a second device interface on the inner surface of the perimeter wall in communication with the second end, the second device interface configured to receive and align a second mobile device configuration with the charging cradle; a cradle interface on an outer surface of the perimeter wall, and configured to couple the adapter to the charging cradle in one of (i) a first orientation to expose a connector of the charging cradle via the first end of the channel, and (ii) a second orientation to expose the connector via the second end of the channel.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: June 4, 2024
    Assignee: Zebra Technologies Corporation
    Inventors: Mu-Kai Shen, Liao-Hsun Chen, Chao Yu Chang
  • Patent number: 12001026
    Abstract: A head-mounted display includes a display device, a connecting structure and a head abutting portion. The connecting structure is in a shape of strip. The connecting structure has two opposite ends. The ends are respectively connected with the display device. The connecting structure and the display device define an accommodation space. The accommodation space is configured to accommodate a head of a user. The head abutting portion is pivotally connected with the connecting structure. The head abutting portion is at least partially located between the connecting structure and the display device. The head abutting portion is configured to abut against the head of the user.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: June 4, 2024
    Assignee: Quanta Computer Inc.
    Inventors: Hung-Yu Lin, Chun-Feng Yeh, Jia-Cheng Chang, Bing-Kai Huang, Chun-Nan Huang, Chun-Lung Chen
  • Patent number: 12002883
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first drift region, a first source/drain region, and a gate oxide layer. The gate structure and the gate oxide layer are disposed on the semiconductor substrate. The first drift region is disposed in the semiconductor substrate. The first source/drain region is disposed in the first drift region. At least a part of a first portion of the gate oxide layer is disposed between the gate structure and the semiconductor substrate in a vertical direction. A second portion of the gate oxide layer is disposed between the first portion and the first source/drain region in a horizontal direction. The second portion includes a bottom extending downwards and a first depressed top surface located above the bottom. A part of the first drift region is located under the first portion and the second portion of the gate oxide layer.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: June 4, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Yu Yang, Shin-Hung Li, Ruei-Jhe Tsao, Che-Hua Chang
  • Patent number: 12002710
    Abstract: A semiconductor structure and method of forming the same are provided. The method includes: forming a plurality of mandrel patterns over a dielectric layer; forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer; removing the plurality of mandrel patterns; patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and forming conductive lines laterally aside the dielectric layer.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: June 4, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsin Chan, Jiing-Feng Yang, Kuan-Wei Huang, Meng-Shu Lin, Yu-Yu Chen, Chia-Wei Wu, Chang-Wen Chen, Wei-Hao Lin, Ching-Yu Chang
  • Publication number: 20240178328
    Abstract: Embodiments include a Schottky barrier diode (SBD) structure and method of forming the same, the SBD structure including a current blockage feature to inhibit current from leaking at an interface with a shallow trench isolation regions surrounding an anode region of the SBD structure.
    Type: Application
    Filed: May 1, 2023
    Publication date: May 30, 2024
    Inventors: Cheng-Hsien Wu, Chien-Lin Tseng, Sheng Yu Lin, Ting-Chang Chang, Yung-Fang Tan, Yu-Fa Tu, Wei-Chun Hung
  • Publication number: 20240176335
    Abstract: A fault detection method, includes the following steps. A target sequence is received, the target sequence includes several data. A first moving average operation is performed on the target sequence to establish a first moving average sequence. A second moving average operation is performed on the target sequence to establish a second moving average sequence. A difference operation between the first moving average sequence and the second moving average sequence is performed to obtain a difference sequence, the difference sequence includes several difference values. An upper limit value is set. When one of the difference values is greater than the upper limit value, the target sequence is determines as abnormal.
    Type: Application
    Filed: February 6, 2024
    Publication date: May 30, 2024
    Inventors: Yung-Yu Yang, Kang-Ping Li, Chih-Kuan Chang, Chung-Chih Hung, Chen-Hui Huang, Nai-Ying Lo, Shih-Wei Huang
  • Publication number: 20240176159
    Abstract: An optical system that includes a first module is provided. The first module includes a first movable portion, a first fixed portion, and a first driving assembly. The first movable portion is configured to connect the first optical member, and is movable relative to the first fixed portion. The first driving assembly is configured to drive the first movable portion to move relative to the first fixed portion.
    Type: Application
    Filed: November 28, 2023
    Publication date: May 30, 2024
    Inventors: Chia-Che WU, Chao-Chang HU, Yung-Hsien YEH, Chih-Wei WENG, Chih-Wen CHIANG, Yu-Chiao LO, Sin-Jhong SONG
  • Publication number: 20240176094
    Abstract: An optical system is provided, including a first module configured to hold a first optical member. The first module includes a first movable portion, a first fixed portion, and a first driving assembly. The first movable portion is configured to connect the first optical member, and is movable relative to the fixed portion. The first driving assembly is configured to drive the first movable portion to move relative to the fixed portion.
    Type: Application
    Filed: November 28, 2023
    Publication date: May 30, 2024
    Inventors: Chia-Che WU, Chao-Chang HU, Yung-Hsien YEH, Chih-Wei WENG, Chih-Wen CHIANG, Yu-Chiao LO, Sin-Jhong SONG
  • Publication number: 20240178102
    Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.
    Type: Application
    Filed: April 21, 2023
    Publication date: May 30, 2024
    Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
  • Publication number: 20240177893
    Abstract: An over-current protection device includes a heat-sensitive layer and an electrode layer. The electrode layer includes a top metal layer and a bottom metal layer, and the heat-sensitive layer attached therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a polymer matrix and a conductive filler. The polymer matrix includes a polyolefin-based homopolymer and a polyolefin-based copolymer. The polyolefin-based homopolymer has a first coefficient of thermal expansion (CTE), and the polyolefin-based copolymer has a second CTE lower than the first CTE. The polyolefin-based homopolymer and the polyolefin-based copolymer together form an interpenetrating polymer network (IPN).
    Type: Application
    Filed: May 3, 2023
    Publication date: May 30, 2024
    Inventors: CHENG-YU TUNG, Chia-Yuan Lee, HSIU-CHE YEN, CHEN-NAN LIU, YUNG-HSIEN CHANG, Yao-Te Chang, FU-HUA CHU, Takashi Hasunuma
  • Publication number: 20240178069
    Abstract: Semiconductor device structures and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack formed over the substrate. The semiconductor device structure further includes a source/drain structure formed adjacent to the gate stack and a contact structure vertically overlapping the source/drain structure. In addition, the contact structure has a first sidewall slopes downwardly from its top surface to its bottom surface, and an angle between the first sidewall and a bottom surface of the contact structure is smaller than 89.5°.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 30, 2024
    Inventors: Lin-Yu HUANG, Sheng-Tsung WANG, Jia-Chuan YOU, Chia-Hao CHANG, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
  • Publication number: 20240173034
    Abstract: Systems, apparatuses, and methods disclosed herein may be directed to clips for medical implementation, including clips for a portion of a heart. The clips may be configured to close the portion of the heart, to reduce blood flow therethrough as well as passage of clots or other undesired materials. In examples, the clips may be configured to close the left atrial appendage (LAA). The closure of the LAA may reduce the possibility of stroke or other maladies stemming from fluid flow with the LAA. In examples, the clips may be positioned exterior of the LAA, to extend over an outer surface of the LAA for closure.
    Type: Application
    Filed: February 2, 2024
    Publication date: May 30, 2024
    Inventors: Harvey H. Chen, Manouchehr A. Miraki, Rodolfo Rodriguez, Erin E. Castioni, Maria L. Saravia, Stephen Epstein, Luke Anthony Zanetti, Ashley Nicolette Hinga (formerly Keffer), Stephen Cournane, Felino V. Cortez, JR., Nancy Ling Chung, Daniel Yasevac, Andrew Ryan, Slava Arabagi, Jaime L. Baluyot, Sooji Van Echten, Da-Yu Chang, John Richard Carpenter, Sai Prasad Uppalapati, Pui Tong Ho, Jason Thai Le, Adam J. Yestrepsky
  • Publication number: 20240178177
    Abstract: A structure includes a redistribution structure, which includes a bottom layer and a plurality of upper layers over the bottom layer. The redistribution structure also includes a power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers, and a metal pad in the bottom layer and overlapped by the power-ground macro. The metal pad is electrically disconnected from the power-ground macro.
    Type: Application
    Filed: January 31, 2024
    Publication date: May 30, 2024
    Inventors: Ting-Yu Yeh, Chun-Hua Chang, Fong-Yuan Chang, Jyh Chwen Frank Lee
  • Publication number: 20240176093
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
  • Publication number: 20240177887
    Abstract: A core wire includes: an inner conductor; and an insulating layer covering the inner conductor, wherein the insulation layer is made by 3D printing process, the insulating layer includes a first semi-insulating layer and a second semi-insulating layer, each of the first semi-insulating layer and the second semi-insulating layer has a groove that matchingly accommodates the shape of the inner conductor, and the first semi-insulating layer and the second semi-insulating layer are combined together.
    Type: Application
    Filed: November 25, 2023
    Publication date: May 30, 2024
    Applicant: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: CHUN-LIN LEE, Jian-Guo Cai, Juan Zheng, Lu-Yu Chang