Abstract: A shift register, a gate drive circuit and a display device. During forward scanning, the first input circuit supplies a signal of a first reference signal terminal to a first node in response to a signal of a first input signal terminal at an input phase, and the second input circuit supplies a signal of a second reference signal terminal to the first node in response to a signal of a second input signal terminal at a reset phase; and during reverse scanning, the second input circuit supplies the signal of the second reference signal terminal to the first node in response to the signal of the second input signal terminal at the input phase, and the first input circuit supplies the signal of the first reference signal terminal to the first node in response to the signal of the first input signal terminal at the reset phase.

Abstract: An array substrate has a display area and a bonding region. The display area includes a distal region, a proximal region, and a middle region therebetween. The array substrate includes a base, a common electrode located in the display area, a connecting lead disposed outside the distal region, a conductive frame at least partially surrounding the display area, and at least one first common signal line, at least one second common signal line and at least one third common signal line. The first common signal line, the second common signal line and the third common signal line are respectively coupled to portions of the common electrode located in the distal region, the proximal region and the middle region. The first common signal line is coupled to the connecting lead. The connecting lead and the portion of the common electrode located in the distal region are coupled to the conductive frame.

Abstract: Embodiments of the present disclosure provide methods for forming merged source/drain features from two or more fin structures. The merged source/drain features according to the present disclosure have a merged portion with an increased height percentage over the overall height of the source/drain feature. The increase height percentage provides an increased landing range for source/drain contact features, therefore, reducing the connection resistance between the source/drain feature and the source/drain contact features. In some embodiments, the emerged source/drain features include one or more voids formed within the merged portion.

Abstract: A method for establishing a 3D medical imaging model of a subject is to be implemented by an X-ray computed tomography (CT) scanner and a processor. The method includes: emitting X-rays on the subject sequentially from plural angles with respect to the subject to obtain M number of X-ray images of the subject in sequence; obtaining, for each pair of consecutive X-ray images, K number of intermediate image(s) by using the pair of consecutive X-ray images as inputs to a convolutional neural network (CNN) model that has been trained for frame interpolation; and establishing the 3D medical imaging model by using a 3D reconstruction technique based on the M number of X-ray images and the intermediate images obtained for the M number of X-ray images.

Abstract: Systems, methods, and devices implement supplemental scanning for establishing network connections in wireless networks. Methods include sending a request to a wireless device, the request including a plurality of scanning parameters, the plurality of scanning parameters identifying a plurality of requested wireless network parameters. Methods also include receiving a reply from the wireless device, the reply including a result of one or more scanning operations performed based on the plurality of scanning parameters. Methods further include selecting, using one or more processors, one or more network connection operations based, at least in part, on the result of the one or more scanning operations, the one or more network connection operations identifying a timing relative to a plurality of wireless projection packets. Methods additionally include performing, using the one or more processors, the one or more network connection operations based, at least in part, on the identified timing.

Abstract: A structure includes a stepped crystalline substrate that includes an upper step, a lower step, and a step rise. A first fin includes a crystalline structure having a first lattice constant. The first fin is formed over the lower step. A second fin includes a crystalline structure having a second lattice constant, the second lattice constant being different than the first lattice constant. The second fin can be formed over the upper step apart from the first fin. A second crystalline structure can be formed over the first crystalline structure and the tops of the fins aligned. The first and second fins can be made of the same material, but with different heights and different channel strain values. The first fin can be used as an NMOS fin and the second fin can be used as a PMOS fin of a CMOS FinFET.

Abstract: An array substrate includes a first base substrate, an insulating layer group, a second electrode, a transparent conductive layer, and a first electrode; the transparent conductive layer and the first electrode are laminated and formed on the same side of the first base substrate; the first electrode has a first opening; the insulating layer group is arranged on a side of the first electrode or the transparent conductive layer away from the first base substrate; the second electrode is arranged on a side of the insulating layer group away from the first base substrate, the second electrode is arranged opposite to the first opening.

Abstract: The present disclosure relates to the field of display technologies, and discloses a display panel, a preparation method thereof, and a display device; the display panel has a display area and a non-display area adjacent to the display area, and the display panel includes an array substrate, an opposite substrate, and a first alignment film and a retaining wall structure; a bonding electrode is arranged on the array substrate, and located in the non-display area; the opposite substrate and the array substrate are arranged opposite to each other; the first alignment film is arranged on a side of the array substrate close to the opposite substrate; the retaining wall structure is arranged on the side of the array substrate close to the opposite substrate, and at least part of the retaining wall structure is located between the first alignment film and the bonding electrode.

Abstract: In some implementations, a control device may determine a spacing measurement in a first dimension between a wafer on a susceptor and a pre-heat ring of a semiconductor processing tool and/or a gapping measurement in a second dimension between the wafer and the pre-heat ring, using one or more images captured in situ during a process by at least one optical sensor. Accordingly, the control device may generate a command based on a setting associated with the process being performed by the semiconductor processing tool and the spacing measurement and/or the gapping measurement. The control device may provide the command to at least one motor to move the susceptor.

Abstract: An array substrate has a display area and a bonding region. The display area includes a distal region away from the bonding region. The array substrate includes a base, a common electrode located in the display area, and at least one first common signal line and at least one feedback signal line that are disposed on the base. The at least one first common signal line and the at least one feedback signal line are coupled to a portion of the common electrode located in the distal region, and extend to the bonding region to be coupled to a circuit board. A feedback signal line transmits a common voltage signal of the portion of the common electrode located in the distal region to the circuit board. A first common signal line transmits a first compensation common voltage signal to the portion of the common electrode located in the distal region.

Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.

Abstract: Some embodiments of the invention provide a method for defining code-based policies. The method generates a policy-builder first view of a policy for display in a graphical user interface (GUI) by processing a syntax tree that is generated from a code second view of the policy. The method receives, through the policy-builder first view, a modification to a portion of the policy. To reflect the modification, the method updates a portion of the syntax tree that corresponds to the portion of the policy that is affected by the modification. Based on the updating of the syntax tree, the method updates the code second view by modifying a portion of the code second view that corresponds to the updated portion of the syntax tree.

Abstract: Systems, methods, and devices implement supplemental scanning for establishing network connections in wireless networks. Methods include sending a request to a wireless device, the request including a plurality of scanning parameters, the plurality of scanning parameters identifying a plurality of requested wireless network parameters. Methods also include receiving a reply from the wireless device, the reply including a result of one or more scanning operations performed based on the plurality of scanning parameters. Methods further include selecting, using one or more processors, one or more network connection operations based, at least in part, on the result of the one or more scanning operations, the one or more network connection operations identifying a timing relative to a plurality of wireless projection packets. Methods additionally include performing, using the one or more processors, the one or more network connection operations based, at least in part, on the identified timing.

Abstract: A structure includes a stepped crystalline substrate that includes an upper step, a lower step, and a step rise. A first fin includes a crystalline structure having a first lattice constant. The first fin is formed over the lower step. A second fin includes a crystalline structure having a second lattice constant, the second lattice constant being different than the first lattice constant. The second fin can be formed over the upper step apart from the first fin. A second crystalline structure can be formed over the first crystalline structure and the tops of the fins aligned. The first and second fins can be made of the same material, but with different heights and different channel strain values. The first fin can be used as an NMOS fin and the second fin can be used as a PMOS fin of a CMOS FinFET.

Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.

Abstract: An array substrate includes a substrate, a gate line on the substrate, a sub-pixel, two data lines, a touch signal line, a functional electrode, and a touch electrode unit. The orthographic projection of the touch signal line on the substrate partially overlaps orthographic projection of an opening area of the sub-pixel on the substrate; the touch electrode unit is coupled to the touch signal line; the extension directions of the first and second sub-function electrode portions of the functional electrode are the same as that of the data line, the first/second sub-functional electrode portion is located on a first/second side of the sub-pixel opening area; along the extending direction of the gate line, a distance between the first/second sub-functional electrode portion and the touch signal line is smaller than a distance between the data line on the first/second side and the touch signal line.

Abstract: Some embodiments of the invention provide a method for defining code-based policies. The method generates a policy-builder first view of a policy for display in a graphical user interface (GUI) by processing a syntax tree that is generated from a code second view of the policy. The method receives, through the policy-builder first view, a modification to a portion of the policy. To reflect the modification, the method updates a portion of the syntax tree that corresponds to the portion of the policy that is affected by the modification. Based on the updating of the syntax tree, the method updates the code second view by modifying a portion of the code second view that corresponds to the updated portion of the syntax tree.

Abstract: Embodiments of the present disclosure provide methods for forming merged source/drain features from two or more fin structures. The merged source/drain features according to the present disclosure have a merged portion with an increased height percentage over the overall height of the source/drain feature. The increase height percentage provides an increased landing range for source/drain contact features, therefore, reducing the connection resistance between the source/drain feature and the source/drain contact features. In some embodiments, the emerged source/drain features include one or more voids formed within the merged portion.

Abstract: The present disclosure discloses a data annotation method and apparatus, an electronic device and a readable storage medium, and relates to artificial intelligence fields such as deep learning, computer vision and autonomous driving. The method may include: acquiring a detection model, the detection model being trained by using sensor data manually annotated as startup data; performing obstacle detection on to-be-annotated sensor data by using the detection model, the startup data and the to-be-annotated sensor data being a same type of sensor data; performing obstacle tracking and matching according to detection results to obtain obstacle trajectory information; and modifying the detection results according to the obstacle trajectory information, and taking modified detection results as required annotation results. Labor and time costs can be saved by use of the solutions of the present disclosure.

Abstract: A shift register circuit includes a first pull-down control sub-circuit and a first noise reduction sub-circuit. The first pull-down control sub-circuit includes a first transistor and a second transistor, and a ratio of a width-to-length ratio of a channel of the second transistor to a width-to-length ratio of a channel of the first transistor is greater than 5:1. The first pull-down control sub-circuit transmits, in response to a first voltage signal received at a first voltage signal terminal, the first voltage signal to a first pull-down node through the first transistor, and transmits a second voltage signal received at a second voltage signal terminal to the first pull-down node through the second transistor under control of a voltage of a pull-up node. The first noise reduction sub-circuit transmits the second voltage signal to the pull-up node under control of a voltage of the first pull-down node.