Patents by Inventor An YU

An YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250120113
    Abstract: A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.
    Type: Application
    Filed: December 17, 2024
    Publication date: April 10, 2025
    Inventors: Ching-Feng Fu, Guan-Ren Wang, Yun-Min Chang, Yu-Lien Huang
  • Publication number: 20250120092
    Abstract: An MRAM structure includes a first memory unit and a second memory unit. A conductive line is disposed between the first memory unit and the second memory unit. An SOT metal conductive line contacts and electrically connects an end of the first memory unit, an end of the conductive line and an end of the second memory unit. A first switch element is electrically connected to an end of the SOT metal conductive line, and a second switch element is electrically connected to the other end of the SOT metal conductive line. A third switch element is electrically connected to the other end of the first memory unit. A fourth switch element is electrically connected to the other end of the conductive line. A fifth switch element is electrically connected to the other end of the second memory unit.
    Type: Application
    Filed: November 13, 2023
    Publication date: April 10, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Fu-Yu Tsai, Bin-Siang Tsai
  • Publication number: 20250120023
    Abstract: A communication device includes a case, a cover, a signal processing module and a signal switching module. The cover whereon the signal processing module is disposed is detachably assembled with the case. The signal switching module is disposed on the case and includes a connection component and a conductive component. The connection element includes a switching element, a chamber, a device port and a module port. The device port is connected to external devices. The switching element is movably disposed inside the chamber. The conductive component is located inside the case, and is spaced from the device port by the switching element when a signal transmission terminal of the signal processing module is inserted into the module port, and further contacts against the device port when the signal transmission terminal is removed from the module port, so as to maintain signal transmission between external devices.
    Type: Application
    Filed: November 7, 2023
    Publication date: April 10, 2025
    Applicant: TCC RFTECH Co., Ltd.
    Inventor: Yu-Kuang Chen
  • Publication number: 20250120091
    Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.
    Type: Application
    Filed: December 18, 2024
    Publication date: April 10, 2025
    Inventors: Kuo-Chang Chiang, Hung-Chang Sun, Sheng-Chih Lai, TsuChing Yang, Yu-Wei Jiang
  • Publication number: 20250119825
    Abstract: Apparatus, methods, and computer-readable media for facilitating determining or predicting a communication state of a UE based on, for example, measurements performed at the UE are disclosed herein. The communication state of the UE, such as an HST state or a non-HST state, may also be associated with a mobility state, such as stationary or moving. The UE may communicate based on the communication state. An example method for wireless communication at a UE includes establishing a connection with a network node. The example method also includes measuring one or more signals received from the network node over a time period. The example method also includes communicating with the network node based on a communication state of the UE, the communication state of the UE based at least in part on a history of measurements performed on the one or more signals received over the time period.
    Type: Application
    Filed: March 29, 2022
    Publication date: April 10, 2025
    Inventors: Jie MAO, Hong YU, Wei LI, Nanrun WU, Jie ZHU, Xinyu WANG, Tom CHIN
  • Publication number: 20250119960
    Abstract: A hotspot communication stabilization system includes a hotspot communication stabilizer. The hotspot communication stabilizer includes a connected device address search unit and a comparator. The connected device address search unit serves to obtain at least one connection address from a communication host device at regular or irregular intervals. The connection address is an address of a peripheral communication device connected to the communication host device and is stored in a connection address table. The comparator serves to determine whether there is a missing address in the connection address table at a current time by comparing two connection addresses of the peripheral communication device at two adjacent times. The missing address is sent to the communication host device and the communication host device re-establishes a hotspot signal connection to the missing address corresponded to a corresponding peripheral communication device.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 10, 2025
    Inventors: YAO CHING WANG, YI CHIEH CHEN, YU NING LAN
  • Publication number: 20250119841
    Abstract: A method for performing mapping between one or more radio modules and one or more radiofrequency (RF) groups includes: separating the one or more radio modules into the one or more RF groups according to one or more messages, wherein the one or more messages comprise a previous TX power ratio, a TX power ratio margin, one or more weighting information, one or more TX performance indices, one or more receiving (RX) performance indices, one or more configurations, or one or more usage scenarios; accumulating RF exposure of the one or more radio modules to at least one RF group among the one or more RF groups; and determining at least one transmitting (TX) power limit corresponding to the at least one RF group according to accumulated RF exposure of the at least one RF group.
    Type: Application
    Filed: October 1, 2024
    Publication date: April 10, 2025
    Applicant: MEDIATEK INC.
    Inventors: Tsung-Po Yu, Yi-Hsuan Lin, Fu-Tse Kao
  • Publication number: 20250119975
    Abstract: The present application provides a method and a device in a communication node for wireless communications. A communication node receives a first message, the first message comprises at least a first information block, the first information block comprises at least a first identifier, the first information block is indicated to perform a data transmission in RRC_INACTIVE state; if any condition in the first condition set is not satisfied, determines performing a data transmission in the RRC_INACTIVE state; if each condition in the first condition set is satisfied, determines that a data transmission in the RRC_INACTIVE state is not performed; the first condition set includes: the first message comprising a second information block, the second information block comprising at least a second identifier, the second identifier being associated with the first node, and the second information block not being indicated to perform a data transmission in the RRC_INACTIVE state.
    Type: Application
    Filed: December 18, 2024
    Publication date: April 10, 2025
    Applicant: SHANGHAI LANGBO COMMUNICATION TECHNOLOGY COMPANY LIMITED
    Inventors: Qiaoling YU, Xiaobo ZHANG
  • Patent number: 12272972
    Abstract: A long-term high-power battery system with intelligent management includes a battery cell, and a battery management system including a secondary control system, a low-power switching element, a high-capacity relay and a battery cell voltage balancing system. When the secondary control system detects a high current load generated by the vehicle startup, the low-power switching element first interrupts the high load connected to the battery management system, and immediately starts the high-capacity relay, so that the large current passes through the high-capacity relay to provide the large current required by the vehicle load equipment. Through the battery cell voltage balancing system, the voltage difference between each battery cell is effectively controlled.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: April 8, 2025
    Inventors: Kuo-Hsin Su, Ta-Yu Su, Hsun-I Lee
  • Patent number: 12272712
    Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having a chip region and a scribe-line region surrounding the chip region and forming a dielectric layer on an upper surface of the substrate. A dummy structure is formed in the dielectric layer over the scribe-line region of the substrate and extends along edges of the chip region. The dummy structure includes a first stack of dummy metal layers and a second stack of dummy metal layers arranged concentrically from the inside to the outside. The method also includes performing a sawing process on a portion of the dielectric layer that surrounds the dummy structure, so as to form a saw opening through the dielectric layer. At least the first stack of dummy metal layers remains in the dielectric layer after the sawing process is performed.
    Type: Grant
    Filed: May 14, 2022
    Date of Patent: April 8, 2025
    Assignee: Xintec Inc.
    Inventors: Tsang-Yu Liu, Chaung-Lin Lai, Shu-Ming Chang
  • Patent number: 12272928
    Abstract: An optical transmission module includes a housing having a cavity therein and an optical transmission device encapsulated in the cavity. The optical transmission device includes an optical waveguide substrate, laser assemblies, an optical multiplexing assembly and main waveguides. The optical waveguide substrate includes a surface and a first reflection inclined surface having an acute angle therebetween. The laser assemblies are disposed on the surface of the optical waveguide substrate, and are configured to emit laser beams towards the surface of the optical waveguide substrate. The optical multiplexing assembly is disposed in the optical waveguide substrate, and is configured to combine the laser beams into a laser beam. The main waveguides are disposed inside the optical waveguide substrate, light inlet ends of the main waveguides face the first inclined surface, and light outlet ends of the main waveguides are communicated with the optical multiplexing assembly.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: April 8, 2025
    Assignee: HISENSE BROADBAND MULTIMEDIA TECHNOLOGIES CO., LTD.
    Inventors: Yi Tang, Jinlei Chen, Feng Cui, Yifan Xie, Qinhao Fu, Lin Yu
  • Patent number: 12272708
    Abstract: An image sensor device includes a semiconductor device, a plurality of photo sensitive regions, a dielectric layer, a grid structure, and a plurality of convex dielectric lenses. The photo sensitive regions are in the semiconductor substrate. The dielectric layer is over a backside surface of the semiconductor substrate. The grid structure is over a backside surface of the dielectric layer. The grid structure includes a plurality of grid lines. Each of the grid lines comprises a lower portion and an upper portion forming an interface with the lower portion. The convex dielectric lenses are alternately arranged with the grid lines over the backside surface of the dielectric layer. Apexes of the plurality of convex dielectric lenses are higher than an interface between the upper portion and the lower portion of each of the grid lines.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: April 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko Jangjian, Chih-Nan Wu, Chun-Che Lin, Yu-Ku Lin
  • Patent number: 12273031
    Abstract: A constant time buck-boost switching converter includes: a power switch circuit for switching a first terminal of an inductor between an input voltage and a ground, and for switching a second terminal of the inductor between an output voltage and the ground; and a modulation control circuit for generating a buck ramp signal and a boost ramp signal and for controlling the inductor according to comparisons of these two ramp signals with an error amplification signal, so as to convert the input voltage to the output voltage. The average levels of the buck ramp signal and the boost ramp signal are both equal to a product of the output voltage multiplied by a predetermined ratio. The upper limit of the buck ramp signal and the lower limit of the boost ramp signal are both equal to a product of the input voltage multiplied by the predetermined ratio.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: April 8, 2025
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Hung-Yu Cheng, Tsung-Han Yu, Keng-Hong Chu
  • Patent number: 12272612
    Abstract: A semiconductor package module includes a package, a conductive layer, and a heat dissipating module. The package includes a semiconductor die. The conductive layer is disposed over the package. The heat dissipating module is disposed over the conductive layer, and the package and the heat dissipating module prop against two opposite sides of the conductive layer, where the heat dissipating module is thermally coupled to and electrically isolated from the package through the conductive layer.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Tsung-Yu Chen
  • Patent number: 12272613
    Abstract: A semiconductor device includes an integrated circuit structure and a thermal pillar over the integrated circuit structure. The integrated circuit structure includes a semiconductor substrate including circuitry, a dielectric layer over the semiconductor substrate, an interconnect structure over the dielectric layer, and a first thermal fin extending through the semiconductor substrate, the dielectric layer, and the interconnect structure. The first thermal fin is electrically isolated from the circuitry. The thermal pillar is thermally coupled to the first thermal fin.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ming Wang, Yu-Hung Lin, Shih-Peng Tai, Kuo-Chung Yee
  • Patent number: 12272594
    Abstract: The present disclosure relates to a semiconductor device and a method of fabricating the same, the semiconductor device including a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate, including a plurality of first active fragments and a plurality of second active fragments. The first active fragments and the second active fragments are parallel and separately extended along a first direction, and the second active fragments are disposed outside all of the first active fragments. The first active fragments have a same length in the first direction, being a first length, the second active fragment have a second length in the first direction, and the second length is greater than the first length.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: April 8, 2025
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Cheng Tung, Janbo Zhang
  • Patent number: 12272621
    Abstract: The present disclosure describes a buried conductive structure in a semiconductor substrate and a method for forming the structure. The structure includes an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer, a first silicide layer disposed within a top portion of the epitaxial region, and a first conductive structure disposed on a top surface of the first silicide layer. The structure further includes a second silicide layer disposed within a bottom portion of the epitaxial region and a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, where the second conductive structure includes a first metal layer in contact with the second silicide layer and a second metal layer in contact with the first metal layer.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kan-Ju Lin, Lin-Yu Huang, Min-Hsuan Lu, Wei-Yip Loh, Hong-Mao Lee, Harry Chien
  • Patent number: 12272524
    Abstract: A wideband variable impedance load for high volume manufacturing qualification and diagnostic testing of a radio frequency power source, an impedance matching network and RF sensors for generating plasma in a semiconductor plasma chamber for semiconductor fabrication processes. The wideband variable impedance load may comprise a fixed value resistance operable at a plurality of frequencies and coupled with a variable impedance network capable of transforming the fixed value resistance into a wide range of complex impedances at the plurality of frequencies. Response times and match tuning element position repeatability may be verified. Automatic testing, verification and qualification of production and field installed radio frequency power sources for plasma generation are easily performed.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: April 8, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Yue Guo, Kartik Ramaswamy, Jie Yu, Yang Yang
  • Patent number: 12273028
    Abstract: A resonant asymmetrical half-bridge flyback power converter includes: a first transistor and a second transistor switching a transformer coupled to a capacitor for generating an output power; a voltage divider coupled to an auxiliary winding of the transformer; a differential sensing circuit which includes a first terminal and a second terminal coupled to the voltage divider to sense an auxiliary signal generated by the auxiliary winding for generating a peak signal and a demagnetization-time signal; and a PWM control circuit configured to generate a first PWM signal and a second PWM signal in accordance with the peak signal and the demagnetization-time signal, for controlling the first transistor and the second transistor respectively; wherein a period of an enabling state of the demagnetization-time signal is correlated to the output power level; wherein the peak signal is related to a quasi-resonance of the transformer after the transformer is demagnetized.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: April 8, 2025
    Assignee: Richtek Technology Corporation
    Inventors: Ta-Yung Yang, Yu-Chang Chen, Hsin-Yi Wu, Kun-Yu Lin
  • Patent number: 12272554
    Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: April 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jia-Lin Wei, Ming-Hui Weng, Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Yahru Cheng, Jr-Hung Li, Ching-Yu Chang, Tze-Liang Lee, Chi-Ming Yang