Abstract: A thin substrate has a layered structure on one surface, and can also have a layered structure on the other. Each layered structure can include a part of at least one patterned layer that, if patterned by photolithography, would frequently result in damage to the substrate due to fragility. For example, the substrate could be a 3 mil (76.2 ?m) or thinner polyimide film and one patterned layer could be a semiconductor material such as vanadium oxide, while another could be metal in electrical contact with semiconductor material. The layer part, however, can be patterned by a printing operation or can include a printed patterned artifact such as an uneven boundary or an alignment. The printing operation can be direct printing or printing of a mask for etching or liftoff or both. The layered structure can include an array of cells, each with layer parts on each substrate surface.

Abstract: A thin substrate has a layered structure on one surface, and can also have a layered structure on the other. Each layered structure can include a part of at least one patterned layer that, if patterned by photolithography, would frequently result in damage to the substrate due to fragility. For example, the substrate could be a 3 mil (76.2 ?m) or thinner polyimide film and one patterned layer could be a semiconductor material such as vanadium oxide, while another could be metal in electrical contact with semiconductor material. The layer part, however, can be patterned by a printing operation or can include a printed patterned artifact such as an uneven boundary or an alignment. The printing operation can be direct printing or printing of a mask for etching or liftoff or both. The layered structure can include an array of cells, each with layer parts on each substrate surface.

Abstract: A thin substrate has a layered structure on one surface, and can also have a layered structure on the other. Each layered structure can include a part of at least one patterned layer that, if patterned by photolithography, would frequently result in damage to the substrate due to fragility. For example, the substrate could be a 3 mil (76.2 ?m) or thinner polyimide film and one patterned layer could be a semiconductor material such as vanadium oxide, while another could be metal in electrical contact with semiconductor material. The layer part, however, can be patterned by a printing operation or can include a printed patterned artifact such as an uneven boundary or an alignment. The printing operation can be direct printing or printing of a mask for etching or liftoff or both. The layered structure can include an array of cells, each with layer parts on each substrate surface.

Abstract: A thin substrate has a layered structure on one surface, and can also have a layered structure on the other. Each layered structure can include a part of at least one patterned layer that, if patterned by photolithography, would frequently result in damage to the substrate due to fragility. For example, the substrate could be a 3 mil (76.2 ?m) or thinner polyimide film and one patterned layer could be a semiconductor material such as vanadium oxide, while another could be metal in electrical contact with semiconductor material. The layer part, however, can be patterned by a printing operation or can include a printed patterned artifact such as an uneven boundary or an alignment. The printing operation can be direct printing or printing of a mask for etching or liftoff or both. The layered structure can include an array of cells, each with layer parts on each substrate surface.

Abstract: A thin substrate has a layered structure on one surface, and can also have a layered structure on the other. Each layered structure can include a part of at least one patterned layer that, if patterned by photolithography, would frequently result in damage to the substrate due to fragility. For example, the substrate could be a 3 mil (76.2 ?m) or thinner polyimide film and one patterned layer could be a semiconductor material such as vanadium oxide, while another could be metal in electrical contact with semiconductor material. The layer part, however, can be patterned by a printing operation or can include a printed patterned artifact such as an uneven boundary or an alignment. The printing operation can be direct printing or printing of a mask for etching or liftoff or both. The layered structure can include an array of cells, each with layer parts on each substrate surface.

Abstract: An organic non-volatile memory array including multiple pixels and associated signal lines that are disposed on and between a substrate, a single ferroelectric dielectric layer, and a single organic dielectric layer, where each pixel includes a ferroelectric field-effect transistor (FeFET) and at least one organic thin-film field effect transistor (FET) that are connected to associated signal lines in a way that facilitates addressable reading and writing to the FeFET of a selected pixel without disturbing the data stored in adjacent pixels. Analog data storage in the FeFET array is also introduced that does not require analog-to-digital conversion of the stored data.

Abstract: A device has a substrate, a piezo polymer layer arranged adjacent the substrate, a first electrode in contact with a first side of the layer, and a second electrode arranged adjacent the first electrode, such that when the piezo layer flexes, the first and second electrodes are arranged to detect one of a change in voltage or resistance, wherein at least one of the piezo polymer layer or the electrodes are deposited by printing. A method including depositing a spacer layer onto a substrate, depositing a piezo polymer layer onto the substrate, patterning an array of first electrodes in contact with the piezo polymer layer, and patterning an array of second electrodes adjacent the array of first electrodes, wherein depositing includes one of printing and laminating and pattering includes one of printing and etching.

Abstract: A method of printing electronic circuits uses pattern recognition to detect locations of interconnects on electronic components oriented on a substrate such that the interconnects face away from the substrate, the interconnects having ramps between the interconnects and the substrate, adjusts routing paths as needed based upon a difference between an intended placement and an actual placement of the electronic components, and generates a new image file for printing with adjusted routing paths. A device has at least one electronic component having interconnects, a ramp from a surface of the substrate to the interconnects, wherein the ramp is formed of one of either a polymer or an adhesive, a printed, conductive path on the ramp providing electrical connection to at least one of the interconnects.

Abstract: A transistor is formed by applying modifier coatings to source and drain contacts and/or to the channel region between those contacts. The modifier coatings are selected to adjust the surface energy pattern in the source/drain/channel region such that semiconductor printing fluid is not drawn away from the channel region. For example, the modifier coatings for the contacts can be selected to have substantially the same surface energy as the modifier coating for the channel region. Semiconductor printing fluid deposited on the channel region therefore settles in place (due to the lack of a surface energy differential) and forms a relatively thick active semiconductor region between the contacts. Alternatively, the modifier coatings can be selected to have lower surface energies than the modifier coating in the channel region, which actually causes semiconductor printing fluid to be drawn towards the channel region.

Abstract: An organic non-volatile memory array including multiple pixels and associated signal lines that are disposed on and between a substrate, a single ferroelectric dielectric layer, and a single organic dielectric layer, where each pixel includes a ferroelectric field-effect transistor (FeFET) and at least one organic thin-film field effect transistor (FET) that are connected to associated signal lines in a way that facilitates addressable reading and writing to the FeFET of a selected pixel without disturbing the data stored in adjacent pixels. Analog data storage in the FeFET array is also introduced that does not require analog-to-digital conversion of the stored data.

Abstract: A method of forming an electronic device includes depositing a dielectric, forming a first functional material layer having a first surface energy, depositing at least one first at least semiconductive feature of the device, forming a second functional material layer to provide a surface having a second surface energy, and depositing at least one second at least semiconductive feature of the device to connect to the first at least semiconductive feature of the device. A method of forming an electronic device includes depositing a first, dielectric material, depositing a second material, depositing at lease one first at least semiconductive feature of the device on the second material, altering the second material to form a altered second material, and depositing at least one at least semiconductive feature from solution to connect the first semiconductive feature of the device.

Abstract: A passive electronic device includes layers of a layered structure on a support surface. The device can include a first layer part that includes electrically conductive or semiconductive material and that has a contact surface. The device can also include second layer parts that include electrically conductive material and are in electrical contact with the contact surface, with a subset electrically connectible to external circuitry. At least one of the parts of the two layers can be produced by a printing operation or can include a printed patterned artifact such as an uneven boundary or an alignment. The printing operation can be direct printing or printing of a mask for etching or liftoff or both. The device could, for example, be a resistive device, such as a device with resistance varying in response to non-electrical stimuli, or a conductive device, such as with a contact pad for a pogo pin.

Abstract: A layered structure is produced on a support structure's surface. The layered structure can include a component that responds electrically to thermal signals, such as a thermistor, and can also include a layer part that has a printed patterned artifact such as an uneven boundary or an alignment. A layered structure can be produced by depositing a layer of material, printing a mask, and removing the exposed part of the layer.

Abstract: A device has a substrate, a piezo polymer layer arranged adjacent the substrate, a first electrode in contact with a first side of the layer, and a second electrode arranged adjacent the first electrode, such that when the piezo layer flexes, the first and second electrodes are arranged to detect one of a change in voltage or resistance, wherein at least one of the piezo polymer layer or the electrodes are deposited by printing. A method including depositing a spacer layer onto a substrate, depositing a piezo polymer layer onto the substrate, patterning an array of first electrodes in contact with the piezo polymer layer, and patterning an array of second electrodes adjacent the array of first electrodes, wherein depositing includes one of printing and laminating and pattering includes one of printing and etching.

Abstract: A method of forming vias and pillars using printed masks is described. The printed masks are typically made from droplets that include suspended metal nanoparticles. The use of the same metal nanoparticle solution in both the mask formation and the subsequent formation of conducting structures simplifies the fabrication process.

Abstract: A method forms a first active electronic layer, prints an array of pillars on the first active electronic layer, dispenses a curable polymer over the array of pillars, molds the curable polymer by contacting the curable polymer with a mold structure to displace the curable polymer from upper surfaces of the pillars, cures the curable polymer to produce a hardened polymer, and removes the array of pillars to leave an array of holes in the hardened polymer. Another method provides a substrate having selected areas, prints an array of pillars on the substrate, dispenses a curable polymer over the array of pillars, molds the curable polymer by contacting the array of pillars with a mold structure to displace the curable polymer from upper surfaces of the pillars, cures the curable polymer to produce a hardened polymer, and removes the array of pillars to leave an array of holes in the hardened polymer corresponding to the selected areas.

Abstract: A method forms a first active electronic layer, prints an array of pillars on the first active electronic layer, dispenses a curable polymer over the array of pillars, molds the curable polymer by contacting the curable polymer with a mold structure to displace the curable polymer from upper surfaces of the pillars, cures the curable polymer to produce a hardened polymer, and removes the array of pillars to leave an array of holes in the hardened polymer. Another method provides a substrate having selected areas, prints an array of pillars on the substrate, dispenses a curable polymer over the array of pillars, molds the curable polymer by contacting the array of pillars with a mold structure to displace the curable polymer from upper surfaces of the pillars, cures the curable polymer to produce a hardened polymer, and removes the array of pillars to leave an array of holes in the hardened polymer corresponding to the selected areas.

Abstract: A method of forming an electronic device includes depositing a dielectric, forming a first functional material layer having a first surface energy, depositing at least one first at least semiconductive feature of the device, forming a second functional material layer to provide a surface having a second surface energy, and depositing at least one second at least semiconductive feature of the device to connect to the first at least semiconductive feature of the device. A method of forming an electronic device includes depositing a first, dielectric material, depositing a second material, depositing at least one first at least semiconductive feature of the device on the second material, altering the second material to form a altered second material, and depositing at least one at least semiconductive feature from solution to connect the first semiconductive feature of the device.

Abstract: A method of printing electronic circuits uses pattern recognition to detect locations of interconnects on electronic components oriented on a substrate such that the interconnects face away from the substrate, the interconnects having ramps between the interconnects and the substrate, adjusts routing paths as needed based upon a difference between an intended placement and an actual placement of the electronic components, and generates a new image file for printing with adjusted routing paths. A device has at least one electronic component having interconnects, a ramp from a surface of the substrate to the interconnects, wherein the ramp is formed of one of either a polymer or an adhesive, a printed, conductive path on the ramp providing electrical connection to at least one of the interconnects.

Abstract: A patterned integrated circuit structure defining a gap or via is fabricated solely by digital printing and bulk processing. A sacrificial lift-off pattern is printed or otherwise formed over a substrate, and then covered by a blanket layer. A mask is then formed, e.g., by printing a wax pattern that covers a region of the blanket layer corresponding to the desired patterned structure, and overlaps the lift-off pattern. Exposed portions of the blanket layer are then removed, e.g., by wet etching. The printed mask and the lift-off pattern are then removed using a lift-off process that also removes any remaining portions of the blanket layer formed over the lift-off pattern. A thin-film transistor includes patterned source/drain structures that are self-aligned to an underlying gate structure by forming a photoresist lift-off pattern that is exposed and developed by a back-exposure process using the gate structure as a mask.