Abstract: In a disclosed embodiment, a power line communication (PLC) transmitter includes a forward error correction (FEC) encoder that receives payload data and adds parity information to the data to create an encoded output, a fragmenter that receives the encoded output from the FEC encoder and segments the encoded output into a plurality of fragments, a fragment repetition encoder that receives the plurality of fragments from the fragmenter and copies each of the fragments a selected number of times, and an interleaver that receives the copies of the plurality of fragments from the fragment repetition encoder and interleaves the copies of the plurality of fragments for transmission on a power line.

Abstract: In a disclosed embodiment, a power line communication (PLC) transmitter includes a forward error correction (FEC) encoder that receives payload data and adds parity information to the data to create an encoded output, a fragmenter that receives the encoded output from the FEC encoder and segments the encoded output into a plurality of fragments, a fragment repetition encoder that receives the plurality of fragments from the fragmenter and copies each of the fragments a selected number of times, and an interleaver that receives the copies of the plurality of fragments from the fragment repetition encoder and interleaves the copies of the plurality of fragments for transmission on a power line.

Abstract: A VBUS conductor is checked to determine whether a voltage on the VBUS conductor is greater than a vSafe0V voltage within a detect time interval. A device policy manager applies a vSafeDB voltage to the VBUS conductor when the voltage on the VBUS conductor is greater than the vSafe0V voltage. The policy engine waits for a bit stream to be detected within a timer interval. When the bit stream is not detected within the timer interval, the device policy manager is instructed to apply the vSafe0V voltage to the VBUS conductor. The device policy manager applies a vSafe5V voltage to the VBUS conductor when the bit stream is detected, and the policy engine waits for the bit stream to stop within a device ready timer interval. When the bit stream has stopped within the device ready timer interval, the policy engine sends capabilities as a source port.

Abstract: A frequency modulated continuous wave (FMCW) radar system that includes a transceiver coupled to an analog to digital converter (ADC), and a digital signal processor (DSP) coupled to the ADC. The transceiver is configured to transmit a plurality of FMCW chirps, receive a plurality of reflected FMCW chirps, and mix the reflected FMCW chirps with at least one of the FMCW chirps to generate a plurality of beat signals. The reflected FMCW chirps are the FMCW chirps after being reflected off of a target object. The ADC is configured to convert the beat signals into a plurality of digital chirps. The DSP is configured to receive the digital chirps and quantify a relative velocity of the target object as compared to a velocity of the FMCW radar system by removing an effect of a range to the target object from a two dimensional range Doppler processing signal.

Abstract: A touch screen system includes a capacitive touch screen (1) including a plurality of row conductors (7-1, 2 . . . n) and a column conductor (5-1). A plurality of contemporaneous orthogonal excitation signals (S1(t), S2 (t) . . . Sn(t)) are simultaneously driven onto the row conductors, respectively. The capacitively coupled signals on the column conductor may be influenced by a touch (10) on the capacitive touch screen. Receiver circuitry (50) includes a sense amplifier (21-1) coupled to generate an amplifier output signal (r1(t)) in response to signals capacitively coupled onto the column conductor. WHT-based circuitry (35) determines amounts of signal contribution capacitively coupled by each of the excitation signals, respectively, to the amplifier output signal.

Abstract: In a disclosed embodiment, a power line communication (PLC) transmitter includes a forward error correction (FEC) encoder that receives payload data and adds parity information to the data to create an encoded output, a fragmenter that receives the encoded output from the FEC encoder and segments the encoded output into a plurality of fragments, a fragment repetition encoder that receives the plurality of fragments from the fragmenter and copies each of the fragments a selected number of times, and an interleaver that receives the copies of the plurality of fragments from the fragment repetition encoder and interleaves the copies of the plurality of fragments for transmission on a power line.

Abstract: A flow meter ultrasonically measures fluid velocity in a pipe. Ultrasonic signals received by ultrasonic transducers are digitized. The difference between two ultrasonic propagation times is determined by computing a discrete cross-correlation of the digitized received signals. Computation time is reduced by computing only a few cross-correlation values near a peak cross-correlation value.

Abstract: A method of ultrasound flow metering includes applying a first and second pulse train to an ultrasound transducer pair (T1, T2) positioned for coupling ultrasonic waves therebetween. Responsive to the first pulse train applied to T1, T1 transmits an ultrasonic wave received as received ultrasonic wave (R12) by T2 after propagating through fluid in a pipe. Responsive to the second pulse train applied to T2, T2 transmits an ultrasonic wave received as received ultrasonic wave by (R21) T1 after propagating through the fluid. During the pulse trains, R12 and R21 build up in amplitude to provide excitation portions. The pulse trains are terminated, so that R12 and R21 decay as a damped free oscillation. Windowing is applied to R12 and R21 to generate windowed portions. A signal delay between t12 and t21 (?TOF) is calculated using only windowed portions, and a fluid flow is calculated from the ?TOF.

Abstract: Embodiments of the invention provide a device and a frame structure for powerline communications. The header may comprise two parts that are separately encoded. A common header segment is encoded alone, and an embedded header segment is encoded with payload data.

Abstract: Systems and methods for routing protocols for power line communications (PLC) are described. In some embodiments, a method performed by a PLC device, such as a PLC meter, may include selecting one or more transmit sub-bands on which to transmit frames, where the transmit sub-bands comprise groups of carrier frequencies. The PLC device then generates a frame comprising a tone map that indicates which transmit sub-bands are used to carry data for the frame. The tone map using two bits per transmit sub-band to indicate a status of each transmit sub-band. The PLC device then transmits the frame on the selected transmit sub-bands. A resolution bit and a mode bit may be used to provide additional information about the transmit sub-bands, such as an amount of power adjustment that has been applied to carrier frequencies and whether dummy bits are transmitted on unused carrier frequencies.

Abstract: A method, system and apparatus is disclosed for auto-tuning a circuit associated with an upstream transducer (UPT) and a circuit associated with a downstream transducer (DNT) for reciprocal operation in an ultrasonic flowmeter. The method includes exchanging signals between the upstream transducer and the downstream transducer; comparing at least one of respective maximum amplitudes of an upstream signal and a downstream signal and respective center frequencies of a Fast Fourier Transform (FFT) of the upstream signal and the downstream signal; and responsive to determining that at least one of the respective maximum amplitudes and the respective center frequencies do not match, correcting the mismatch.

Abstract: Systems and methods for relative phase detection and zero crossing detection for power line communications (PLC) are described. In some embodiments, both transmit and receive PLC devices detect a zero crossing on an AC mains phase. The devices start a phase detection counter (PDC) by generating a zero crossing pulse within 5% of the actual zero crossing time. When a frame is transmitted, the transmitting device includes a PDC value in the frame control header (FCH). The PDC value corresponds to the start time of the FCH. When the frame is received at the receive PLC device, the receive PLC device measures a local PDC value between the zero crossing and the start of the FCH. The receive device compares the local PDC value to the PDC value in the FCH of the received frame and determines if the devices are on the same phase.

Abstract: Systems and methods for enabling co-existence among power line communications (PLC) technologies are described. In some embodiments, a method performed by a PLC device, such as a PLC gateway, may include searching for and detecting a co-existence preamble on a PLC network while not transmitting or receiving frames. The device waits a time period before attempting transmission of a frame if the coexistence preamble is detected and is not followed by a native preamble. Transmissions are resumed to the PLC network after expiration of the time period.

Abstract: A transceiver device combination includes a first ultrasound transducer and a processor chip including a central processing unit (CPU). A memory is coupled to the CPU including stored ultrasound communications software for rendering the processor chip a target device for an ultrasound probe driven via a host computing device having a second ultrasound transducer for together performing ultrasonic debugging of the processor chip. The transceiver device combination includes (i) a transmit path including an ultrasound driver having an input driven by an output of the CPU, where an output of the ultrasound driver is coupled to drive an input of the first ultrasound transducer to transmit ultrasound signals and (ii) a receive path including analog signal processing circuitry that couples an output of the first ultrasound transducer responsive to received ultrasound signals from the ultrasound probe to an input of the CPU.

Abstract: A VBUS conductor is checked to determine whether a voltage on the VBUS conductor is greater than a vSafe0V voltage within a detect time interval. A device policy manager applies a vSafeDB voltage to the VBUS conductor when the voltage on the VBUS conductor is greater than the vSafe0V voltage. The policy engine waits for a bit stream to be detected within a timer interval. When the bit stream is not detected within the timer interval, the device policy manager is instructed to apply the vSafe0V voltage to the VBUS conductor. The device policy manager applies a vSafe5V voltage to the VBUS conductor when the bit stream is detected, and the policy engine waits for the bit stream to stop within a device ready timer interval. When the bit stream has stopped within the device ready timer interval, the policy engine sends capabilities as a source port.

Abstract: Systems and methods for enabling co-existence among power line communications (PLC) technologies are described. In some embodiments, a method performed by a PLC device, such as a PLC gateway, may include searching for and detecting a co-existence preamble on a PLC network while not transmitting or receiving frames. The device waits a time period before attempting transmission of a frame if the coexistence preamble is detected and is not followed by a native preamble. Transmissions are resumed to the PLC network after expiration of the time period.

Abstract: Systems and methods for enabling co-existence among power line communications (PLC) technologies are described. In some embodiments, a method performed by a PLC device, such as a PLC gateway, may include detecting a communication from foreign PLC device on a PLC network in response to a foreign preamble received by the PLC device, terminating transmissions to the PLC network for a network-specific co-existence Extended Interframe Space (cEIFS) time period in response to the foreign preamble, and resuming transmissions to the PLC network after expiration of the network-specific time period.

Abstract: A transducer system with a transducer and circuitry for applying a pulse train to excite the transducer. The circuitry for applying a pulse train selects a first set having a first number of pulses at a first frequency and a second set of pulses having a second number of pulses at a second frequency differing from the first frequency. At least one pulse from the first set is located in the pulse train between one or more of the pulses at the second frequency.

Abstract: A frequency modulated continuous wave (FMCW) radar system that includes a transceiver coupled to an analog to digital converter (ADC), and a digital signal processor (DSP) coupled to the ADC. The transceiver is configured to transmit a plurality of FMCW chirps, receive a plurality of reflected FMCW chirps, and mix the reflected FMCW chirps with at least one of the FMCW chirps to generate a plurality of beat signals. The reflected FMCW chirps are the FMCW chirps after being reflected off of a target object. The ADC is configured to convert the beat signals into a plurality of digital chirps. The DSP is configured to receive the digital chirps and quantify a relative velocity of the target object as compared to a velocity of the FMCW radar system by removing an effect of a range to the target object from a two dimensional range Doppler processing signal.

Abstract: A receiver in an OFDM based communication system is adapted to perform channel estimation using a received reference signal transmitted from at least one antenna The reference signal is substantially located into at least two OFDM symbols of a transmission time interval comprising of more than two OFDM symbols. A power level of said reference signal is divided into said non-consecutive OFDM symbols in said transmission time interval and adapted to use the reference signal located in a first OFDM symbol in succeeding transmission time intervals in addition to the reference symbols in a current transmission time interval and a preceding transmission time interval.