Abstract: Systems and methods for enabling co-existence among power line communications (PLC) technologies are described. In some embodiments, a method performed by a PLC device, such as a PLC gateway, may include searching for and detecting a co-existence preamble on a PLC network while not transmitting or receiving frames. The device waits a time period before attempting transmission of a frame if the coexistence preamble is detected and is not followed by a native preamble. Transmissions are resumed to the PLC network after expiration of the time period.

Abstract: A transceiver device combination includes a first ultrasound transducer and a processor chip including a central processing unit (CPU). A memory is coupled to the CPU including stored ultrasound communications software for rendering the processor chip a target device for an ultrasound probe driven via a host computing device having a second ultrasound transducer for together performing ultrasonic debugging of the processor chip. The transceiver device combination includes (i) a transmit path including an ultrasound driver having an input driven by an output of the CPU, where an output of the ultrasound driver is coupled to drive an input of the first ultrasound transducer to transmit ultrasound signals and (ii) a receive path including analog signal processing circuitry that couples an output of the first ultrasound transducer responsive to received ultrasound signals from the ultrasound probe to an input of the CPU.

Abstract: A VBUS conductor is checked to determine whether a voltage on the VBUS conductor is greater than a vSafe0V voltage within a detect time interval. A device policy manager applies a vSafeDB voltage to the VBUS conductor when the voltage on the VBUS conductor is greater than the vSafe0V voltage. The policy engine waits for a bit stream to be detected within a timer interval. When the bit stream is not detected within the timer interval, the device policy manager is instructed to apply the vSafe0V voltage to the VBUS conductor. The device policy manager applies a vSafe5V voltage to the VBUS conductor when the bit stream is detected, and the policy engine waits for the bit stream to stop within a device ready timer interval. When the bit stream has stopped within the device ready timer interval, the policy engine sends capabilities as a source port.

Abstract: Systems and methods for enabling co-existence among power line communications (PLC) technologies are described. In some embodiments, a method performed by a PLC device, such as a PLC gateway, may include searching for and detecting a co-existence preamble on a PLC network while not transmitting or receiving frames. The device waits a time period before attempting transmission of a frame if the coexistence preamble is detected and is not followed by a native preamble. Transmissions are resumed to the PLC network after expiration of the time period.

Abstract: Systems and methods for enabling co-existence among power line communications (PLC) technologies are described. In some embodiments, a method performed by a PLC device, such as a PLC gateway, may include detecting a communication from foreign PLC device on a PLC network in response to a foreign preamble received by the PLC device, terminating transmissions to the PLC network for a network-specific co-existence Extended Interframe Space (cEIFS) time period in response to the foreign preamble, and resuming transmissions to the PLC network after expiration of the network-specific time period.

Abstract: A transducer system with a transducer and circuitry for applying a pulse train to excite the transducer. The circuitry for applying a pulse train selects a first set having a first number of pulses at a first frequency and a second set of pulses having a second number of pulses at a second frequency differing from the first frequency. At least one pulse from the first set is located in the pulse train between one or more of the pulses at the second frequency.

Abstract: A frequency modulated continuous wave (FMCW) radar system that includes a transceiver coupled to an analog to digital converter (ADC), and a digital signal processor (DSP) coupled to the ADC. The transceiver is configured to transmit a plurality of FMCW chirps, receive a plurality of reflected FMCW chirps, and mix the reflected FMCW chirps with at least one of the FMCW chirps to generate a plurality of beat signals. The reflected FMCW chirps are the FMCW chirps after being reflected off of a target object. The ADC is configured to convert the beat signals into a plurality of digital chirps. The DSP is configured to receive the digital chirps and quantify a relative velocity of the target object as compared to a velocity of the FMCW radar system by removing an effect of a range to the target object from a two dimensional range Doppler processing signal.

Abstract: A system is provided for calibrating a device. The system includes a reference component, a sampling component, a calibration component, a comparing component and a proportional integral component. The reference component provides a reference power signal based on a voltage instruction and a current instruction. The sampling component samples a voltage signal to obtain a sampled voltage value and samples a current signal to obtain a sampled current value. The calibration component generates a calibrated power signal based on the sampled voltage value and the sampled current. The comparing component generates an error signal based on the reference power signal and the calibrated power signal. The proportional integral component and the calibration component are a feedback system that is operable to calibrate the gain of the sampled voltage and the sample current based on the error signal.

Abstract: A frequency modulated continuous wave (FMCW) radar system that includes a transceiver coupled to an analog to digital converter (ADC), and a digital signal processor (DSP) coupled to the ADC. The transceiver is configured to transmit a plurality of FMCW chirps, receive a plurality of reflected FMCW chirps, and mix the plurality of reflected FMCW chirps with at least one of the FMCW chirps to generate a plurality of beat signals. The reflected FMCW chirps are the FMCW chirps after being reflected off of a target object. The ADC is configured to convert the beat signals into a plurality of digital chirps. The DSP is configured to receive the digital chirps and quantify a plurality of vibration parameters for the target object based on a comparison of phase information in a frequency domain between one of the plurality of FMCW chirps and one of the plurality of digital chirps.

Abstract: Systems and methods for routing protocols for power line communications (PLC) are described. In some embodiments, a method performed by a PLC device, such as a PLC meter, may include selecting one or more transmit sub-bands on which to transmit frames, where the transmit sub-bands comprise groups of carrier frequencies. The PLC device then generates a frame comprising a tone map that indicates which transmit sub-bands are used to carry data for the frame. The tone map using two bits per transmit sub-band to indicate a status of each transmit sub-band. The PLC device then transmits the frame on the selected transmit sub-bands. A resolution bit and a mode bit may be used to provide additional information about the transmit sub-bands, such as an amount of power adjustment that has been applied to carrier frequencies and whether dummy bits are transmitted on unused carrier frequencies.

Abstract: A method of calculating a time difference is disclosed. The method includes sampling a first ultrasonic signal (r21) to produce a first sampled signal (y1(i)) and sampling a second ultrasonic signal (r12) to produce a second sampled signal (y2(i)). A first time (LEAD_LAG) is determined between a time the first sampled signal crosses a threshold (?1) and a time the second sampled signal crosses the threshold. The first sampled signal is cross correlated with the second sampled signal to produce a second time (SAMP_OFFSET). The time difference is calculated in response to the first and second times.

Abstract: Embodiments of the invention provide a device and a frame structure for powerline communications. The header may comprise two parts that are separately encoded.

Abstract: Embodiments of the invention provide methods for maximizing the bandwidth utilization in the uplink of a communication system supporting time division multiplexing between unicast and multicast/broadcast communication modes during transmission time intervals in the downlink of a communication system. This is accomplished by multiplexing at least unicast control signaling for UL scheduling assignments in TTIs supporting the multicast/broadcast communication mode. Moreover, multiplexing of unicast control signaling can also be accomplished by splitting a symbol of the multicast/broadcast TTI into two shorter symbols with the first of these two shorter symbols carrying at least unicast control signaling and the second of these shorter symbols carrying multicast/broadcast signaling.

Abstract: A transceiver device combination includes a first ultrasound transducer and a processor chip including a central processing unit (CPU). A memory is coupled to the CPU including stored ultrasound communications software for rendering the processor chip a target device for an ultrasound probe driven via a host computing device having a second ultrasound transducer for together performing ultrasonic debugging of the processor chip. The transceiver device combination includes (i) a transmit path including an ultrasound driver having an input driven by an output of the CPU, where an output of the ultrasound driver is coupled to drive an input of the first ultrasound transducer to transmit ultrasound signals and (ii) a receive path including analog signal processing circuitry that couples an output of the first ultrasound transducer responsive to received ultrasound signals from the ultrasound probe to an input of the CPU.

Abstract: Embodiments of the invention provide an interleaver design and header fields for ITU-T G.hnem. The header may comprise two parts that are separately encoded. A common header segment is encoded alone, and an embedded header segment is encoded with payload data. The interleaver operates on blocks having a size based upon a total number of input bits in an FEC codeword block, a total number of bits loaded on symbols that span a half mains cycle, or a maximum fragment size of 3072 bits. The blocks may be repeated before interleaving. Each block and its repetitions may be interleaved together, such as for header data, or each block and repetition may be interleaved separately, such as for payload data. Cyclic padding may be used on each block to create an integer number of symbols for transmission.

Abstract: Systems and methods for enabling co-existence among power line communications (PLC) technologies are described. In some embodiments, a method performed by a PLC device, such as a PLC gateway, may include detecting a communication from foreign PLC device on a PLC network in response to a foreign preamble received by the PLC device, terminating transmissions to the PLC network for a network-specific co-existence Extended Interframe Space (cEIFS) time period in response to the foreign preamble, and resuming transmissions to the PLC network after expiration of the network-specific time period.

Abstract: A multi-channel flow sensing system typically includes first and second flow-sensing transducers arranged in each channel. A data acquisition system is coupled to the first and second transducers of each of the channels. The data acquisition system is arranged to transmit and/or receive a sensing signal from at least one of the first and second transducers of each of the channels. The received sensing signals are sequentially converted and accumulated as data for billing in accordance with the measured flow within each channel. Using common components within the data acquisition system for measuring the various channels reduces costs and increases affordability in cost-sensitive areas.

Abstract: A system is provided for calibrating a device. The system includes a reference component, a sampling component, a calibration component, a comparing component and a proportional integral component. The reference component provides a reference power signal based on a voltage instruction and a current instruction. The sampling component samples a voltage signal to obtain a sampled voltage value and samples a current signal to obtain a sampled current value. The calibration component generates a calibrated power signal based on the sampled voltage value and the sampled current. The comparing component generates an error signal based on the reference power signal and the calibrated power signal. The proportional integral component and the calibration component are a feedback system that is operable to calibrate the gain of the sampled voltage and the sample current based on the error signal.

Abstract: Systems and methods for designing, using, and/or implementing communications in beacon-enabled networks are described. In various implementations, these systems and methods may be applicable to power line communications (PLC). For example, a method may include identifying one of a plurality of orthogonal superframes. The identified superframe may include beacon slots and contention access period (CAP) slots. The beacon slots may follow a sequence of two or more frequency subbands, and the CAP slots may follow the same sequence of two or more frequency subbands. Also, the sequence of two or more frequency subbands may be distinct from other sequences of two or more frequency subbands followed by other beacon slots and CAP slots within others of the plurality of available superframes. The method may then include communicating with another device using the identified superframe.

Abstract: Systems and methods for enabling co-existence among power line communications (PLC) technologies are described. In some embodiments, a method performed by a PLC device, such as a PLC gateway, may include detecting a communication from foreign PLC device on a PLC network in response to a foreign preamble received by the PLC device, terminating transmissions to the PLC network for a network-specific co-existence Extended Interframe Space (cEIFS) time period in response to the foreign preamble, and resuming transmissions to the PLC network after expiration of the network-specific time period.