Patents by Inventor Anand Hariraj Udupa
Anand Hariraj Udupa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240057923Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to detect a pace pulse in an electrocardiogram (ECG) signal. An example apparatus includes programmable circuitry configured to execute instructions to: identify a leading edge of a pulse in an input signal based on an amplitude change; identify a transition time of the leading edge of the pulse; validate the leading edge of the pulse based on the amplitude change and transition time; identify a trailing edge of the pulse; determine a width of the pulse between the leading edge and the trailing edge; and validate the pulse based on the width.Type: ApplicationFiled: May 31, 2023Publication date: February 22, 2024Inventors: Nithin Jose, Anand Hariraj Udupa, Sachin Aithal, Raja Reddy Patukuri, Ashin Antony
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Publication number: 20240027508Abstract: An example apparatus includes: calibration circuitry configured to determine a second current at a second terminal of a second impedance circuit based on a first parasitic capacitance, a first impedance value, a third impedance value, a first voltage, and a second voltage; determine a third voltage at a second terminal of a second impedance circuit based on the first parasitic capacitance, a second impedance value, the third impedance value, the second voltage, and the second current; and determine a second parasitic capacitance between the second terminal of the second impedance circuit and the second terminal of a fifth impedance circuit based on the second current, the third voltage, a third current at the second terminal of the fifth impedance circuit, and a fourth voltage at the second terminal of the fifth impedance circuit.Type: ApplicationFiled: March 30, 2023Publication date: January 25, 2024Inventors: Aatish Chandak, Aravind Miriyala, Midhun Raveendran, Anand Hariraj Udupa, Raja Reddy Patukuri, Prabin Krishna Yadav
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Publication number: 20220416741Abstract: An ECG signal acquisition system includes a first amplifier which has a non-inverting input adapted to be coupled to a first differential input, an inverting input adapted to be coupled to a second differential input, and an output. The system includes first and second biasing resistors coupled between the non-inverting and inverting inputs of the first amplifier. The system includes an average estimation circuit which has a first input coupled to the non-inverting input of the first amplifier and a second input coupled to the inverting input of the first amplifier. The system includes a driver amplifier which has an inverting input coupled to the output of the average estimation circuit, a non-inverting input coupled to receive a reference common-mode voltage, and an output. The system includes a low-pass filter coupled between the output of the driver amplifier and the biasing resistors.Type: ApplicationFiled: June 29, 2021Publication date: December 29, 2022Inventors: Sandeep Oswal, Raja Reddy Patukuri, Aravind Miriyala, Anand Hariraj Udupa, Hari Babu Tippana, Aatish Chandak
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Patent number: 10739433Abstract: A system may comprise: an excitation current source; a first electrode coupled to the excitation current source; and a second electrode coupled to the excitation current source. The first and second electrodes may be configured to pass an excitation current from the excitation current source through a human body. First and second calibration resistors may be coupled to and positioned between the excitation current source and the first electrode. Third and fourth calibration resistors may be coupled to and positioned between the excitation current source and the second electrode. The system may also comprise a sensor configured to measure voltages across each of the first, second, third, and fourth calibration resistors.Type: GrantFiled: March 21, 2017Date of Patent: August 11, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anand Hariraj Udupa, Hussam Ahmed, Jagannathan Venkataraman, Sandeep Kesrimal Oswal, Prabin Krishna Yadav, Anand Reghunathan, Kiran Rajmohan
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Patent number: 10362994Abstract: A bio-sensing device (and method) calibrates a time period used to make bio-physical measurements. The device initiates a light source sense phase followed by a first ambient sense phase and a second ambient sense phase. In the light source sense phase, the device is configured to receive a digital value indicative of current through a photodetector while the light source circuit is enabled and in each of the first and second ambient sense phases, the device is configured to receive digital values while the light source circuit is disabled. The device iteratively varies the time period between the phases until the digital value received during the first ambient sense phase is within a threshold of the digital value received during the second ambient sense phase. It then applies the same time separation between the light source sense phase and the ambient phase thereby equalizing the magnitude of the ambient light in the two phases.Type: GrantFiled: October 20, 2016Date of Patent: July 30, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Hussam Ahmed, Jagannathan Venkataraman, Sandeep Kesrimal Oswal, Antoine Lourdes Praveen Aroul, Hari Babu Tippana, Anand Hariraj Udupa
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Patent number: 10145736Abstract: At least some embodiments are directed to a light detection system comprising a photodiode, a transimpedance amplifier (TIA) having a differential output and a differential input coupled across the photodiode, a first bias current source coupled to an anode of the photodiode, and a second bias current source coupled to a cathode of the photodiode. The system also comprises a dynamic control logic coupled to the first and second bias current sources and configured to vary bias currents provided by the first and second bias current sources based on the differential output such that the photodiode is reverse-biased.Type: GrantFiled: April 19, 2017Date of Patent: December 4, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Hussam Ahmed, Jagannathan Venkataraman, Sandeep Kesrimal Oswal, Hari Babu Tippana, Anand Hariraj Udupa
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Patent number: 10111624Abstract: The disclosure provides a circuit for impedance measurement. The circuit includes an excitation source coupled between a first set of input switches. An impedance network is coupled between the first set of input switches and a first set of output switches. The impedance network includes a body impedance and a plurality of electrode impedances. A sense circuit is coupled to the first set of output switches. The sense circuit measures the body impedance and at least one electrode impedance of the plurality of electrode impedances.Type: GrantFiled: March 26, 2018Date of Patent: October 30, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anand Hariraj Udupa, Jagannathan Venkataraman, Hussam Ahmed, Sandeep Kesrimal Oswal
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Publication number: 20180214084Abstract: The disclosure provides a circuit for impedance measurement. The circuit includes an excitation source coupled between a first set of input switches. An impedance network is coupled between the first set of input switches and a first set of output switches. The impedance network includes a body impedance and a plurality of electrode impedances. A sense circuit is coupled to the first set of output switches. The sense circuit measures the body impedance and at least one electrode impedance of the plurality of electrode impedances.Type: ApplicationFiled: March 26, 2018Publication date: August 2, 2018Inventors: Anand Hariraj Udupa, Jagannathan Venkataraman, Hussam Ahmed, Sandeep Kesrimal Oswal
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Patent number: 10006950Abstract: The disclosure provides a circuit for impedance measurement. The circuit includes an excitation source that generates an excitation signal. A switched resistor network is coupled to the excitation source, and generates an output signal in response to the excitation signal. A sense circuit is coupled to the switched resistor network, and generates a sense signal in response to the output signal. A comparator is coupled to the sense circuit, and generates a clock signal in response to the sense signal. A mixer is coupled to the sense circuit, and multiplies the sense signal and the clock signal to generate a rectified signal. A low pass filter is coupled to the mixer and filters the rectified signal to generate an averaged signal. A processor is coupled to the low pass filter and measures a body impedance from the averaged signal.Type: GrantFiled: April 23, 2015Date of Patent: June 26, 2018Assignee: Texas Instruments IncorporatedInventors: Anand Hariraj Udupa, Jagannathan Venkataraman, Hussam Ahmed P, Sandeep Kesrimal Oswal
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Publication number: 20170299429Abstract: At least some embodiments are directed to a light detection system comprising a photodiode, a transimpedance amplifier (TIA) having a differential output and a differential input coupled across the photodiode, a first bias current source coupled to an anode of the photodiode, and a second bias current source coupled to a cathode of the photodiode. The system also comprises a dynamic control logic coupled to the first and second bias current sources and configured to vary bias currents provided by the first and second bias current sources based on the differential output such that the photodiode is reverse-biased.Type: ApplicationFiled: April 19, 2017Publication date: October 19, 2017Inventors: Hussam AHMED, Jagannathan VENKATARAMAN, Sandeep Kesrimal OSWAL, Hari Babu TIPPANA, Anand Hariraj UDUPA
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Publication number: 20170265771Abstract: A system may comprise: an excitation current source; a first electrode coupled to the excitation current source; and a second electrode coupled to the excitation current source. The first and second electrodes may be configured to pass an excitation current from the excitation current source through a human body. First and second calibration resistors may be coupled to and positioned between the excitation current source and the first electrode. Third and fourth calibration resistors may be coupled to and positioned between the excitation current source and the second electrode. The system may also comprise a sensor configured to measure voltages across each of the first, second, third, and fourth calibration resistors.Type: ApplicationFiled: March 21, 2017Publication date: September 21, 2017Inventors: Anand Hariraj UDUPA, Hussam AHMED, Jagannathan VENKATARAMAN, Sandeep Kesrimal OSWAL, Prabin Krishna YADAV, Anand REGHUNATHAN, Kiran RAJMOHAN
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Publication number: 20170245803Abstract: A bio-sensing device (and method) calibrates a time period used to make bio-physical measurements. The device initiates a light source sense phase followed by a first ambient sense phase and a second ambient sense phase. In the light source sense phase, the device is configured to receive a digital value indicative of current through a photodetector while the light source circuit is enabled and in each of the first and second ambient sense phases, the device is configured to receive digital values while the light source circuit is disabled. The device iteratively varies the time period between the phases until the digital value received during the first ambient sense phase is within a threshold of the digital value received during the second ambient sense phase. It then applies the same time separation between the light source sense phase and the ambient phase thereby equalizing the magnitude of the ambient light in the two phases.Type: ApplicationFiled: October 20, 2016Publication date: August 31, 2017Inventors: Hussam AHMED, Jagannathan VENKATARAMAN, Sandeep Kesrimal OSWAL, Antoine Lourdes Praveen AROUL, Hari Babu TIPPANA, Anand Hariraj UDUPA
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Publication number: 20150305648Abstract: The disclosure provides a circuit for impedance measurement. The circuit includes an excitation source that generates an excitation signal. A switched resistor network is coupled to the excitation source, and generates an output signal in response to the excitation signal. A sense circuit is coupled to the switched resistor network, and generates a sense signal in response to the output signal. A comparator is coupled to the sense circuit, and generates a clock signal in response to the sense signal. A mixer is coupled to the sense circuit, and multiplies the sense signal and the clock signal to generate a rectified signal. A low pass filter is coupled to the mixer and filters the rectified signal to generate an averaged signal. A processor is coupled to the low pass filter and measures a body impedance from the averaged signal.Type: ApplicationFiled: April 23, 2015Publication date: October 29, 2015Inventors: Anand Hariraj Udupa, Jagannathan Venkataraman, Hussam Ahmed, Sandeep Kesrimal Oswal
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Publication number: 20150293045Abstract: The disclosure provides a circuit for impedance measurement. The circuit includes an excitation source coupled between a first set of input switches. An impedance network is coupled between the first set of input switches and a first set of output switches. The impedance network includes a body impedance and a plurality of electrode impedances. A sense circuit is coupled to the first set of output switches. The sense circuit measures the body impedance and at least one electrode impedance of the plurality of electrode impedances.Type: ApplicationFiled: April 10, 2015Publication date: October 15, 2015Inventors: Anand Hariraj Udupa, Jagannathan Venkataraman, Hussam Ahmed, Sandeep Kesrimal Oswal
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Publication number: 20150054560Abstract: DC offset correction is provided with low frequency support. A first input terminal for receiving an input signal is selectively coupled to a resistance and a capacitor that are series coupled between the first input terminal and a corresponding output terminal. In a calibration phase, the series resistance is coupled between the input terminal and the capacitor and an average voltage level of the input is stored on capacitor. In a signal processing phase, the charged capacitor is coupled in series between the input terminal and the output terminal while the resistance is bypassed. The output signal obtained contains the high and low frequency components of the input signal, while the DC offset in the input signal is removed from the output signal. A differential circuit and methods are disclosed. Additional embodiments are disclosed.Type: ApplicationFiled: August 25, 2014Publication date: February 26, 2015Inventors: Sandeep Kesrimal Oswal, Eeshan Miglani, H. Mohammed Shuaeb Fazeel, Pradeep Nair, Anand Hariraj Udupa
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Patent number: 8963607Abstract: DC offset correction is provided with low frequency support. A first input terminal for receiving an input signal is selectively coupled to a resistance and a capacitor that are series coupled between the first input terminal and a corresponding output terminal. In a calibration phase, the series resistance is coupled between the input terminal and the capacitor and an average voltage level of the input is stored on capacitor. In a signal processing phase, the charged capacitor is coupled in series between the input terminal and the output terminal while the resistance is bypassed. The output signal obtained contains the high and low frequency components of the input signal, while the DC offset in the input signal is removed from the output signal. A differential circuit and methods are disclosed. Additional embodiments are disclosed.Type: GrantFiled: August 25, 2014Date of Patent: February 24, 2015Assignee: Texas Instruments IncorporatedInventors: Sandeep Kesrimal Oswal, Eeshan Miglani, H. Mohammed Shuaeb Fazeel, Pradeep Nair, Anand Hariraj Udupa
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Patent number: 8248055Abstract: A voltage reference containing a programmable resistance portion at an output node at which an output reference voltage is provided. The desired magnitude of the programmable portion which provides optimum matching of an output resistance of the voltage reference and a series resistance of an output capacitor of the voltage reference is determined and hard-programmed. As a result, the output voltage of the voltage reference is provided with improved linearity. In an embodiment, the determination of the magnitude of the programmable portion is performed by providing an input to an analog to digital converter (ADC) with the voltage reference driving the ADC. The resistance setting corresponding to the third harmonic being less than a desired threshold is then hard-programmed. In an alternative embodiment, the programmable portion is set to specific resistance dynamically during operation.Type: GrantFiled: May 29, 2008Date of Patent: August 21, 2012Assignee: Texas Instruments IncorporatedInventors: Visvesvaraya Appala Pentakota, Anand Hariraj Udupa
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Patent number: 7898331Abstract: Increasing the input common-mode range of a circuit which accepts differential signals as inputs. Such an increase may be attained by correcting an input signal at continuous levels or at 2 or more discrete levels) without changing the strength represented by the input signal. In an embodiment, the common-mode component of an input signal is measured, and a correction voltage proportional to the difference between the measured common-mode component and a reference voltage, is generated. The correction voltage is coupled to the input terminals of the differential circuit to correct for any deviations from a desired level of common-mode voltage at the input terminals of the differential circuit. The approaches are applied to a switched-capacitor differential amplifier used in a sample-and-hold portion of an ADC.Type: GrantFiled: November 28, 2005Date of Patent: March 1, 2011Assignee: Texas Instruments IncorporatedInventors: Anand Hariraj Udupa, Jagannathan Venkataraman
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Patent number: 7786909Abstract: With high speed analog to digital converters (ADCs), components within the ADC can enter a saturation region when an input exceeded the input range of the ADC, which can cause errors. Here, a sample of an input signal to an ADC is compared with the upper and lower full-scale levels of the ADC. If input overload is detected, inputs to amplifiers in an input stage of the ADC are forced to zero for the duration of the input overload, and are thus prevented from going into saturation. Input overload conditions are signaled directly to an output digital block of the ADC, which provides output digital codes equivalent to either the upper or the lower full scale level depending on whether the input overload is signaled as exceeding the upper level or the lower level. Input overload recovery time of the ADC may thus be minimized.Type: GrantFiled: December 18, 2008Date of Patent: August 31, 2010Assignee: Texas Instruments IncorporatedInventors: Anand Hariraj Udupa, Neeraj Shrivastava, Nitin Agarwal
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Publication number: 20090295363Abstract: A voltage reference containing a programmable resistance portion at an output node at which an output reference voltage is provided. The desired magnitude of the programmable portion which provides optimum matching of an output resistance of the voltage reference and a series resistance of an output capacitor of the voltage reference is determined and hard-programmed. As a result, the output voltage of the voltage reference is provided with improved linearity. In an embodiment, the determination of the magnitude of the programmable portion is performed by providing an input to an analog to digital converter (ADC) with the voltage reference driving the ADC. The resistance setting corresponding to the third harmonic being less than a desired threshold is then hard-programmed. In an alternative embodiment, the programmable portion is set to specific resistance dynamically during operation.Type: ApplicationFiled: May 29, 2008Publication date: December 3, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Visvesvaraya Appala Pentakota, Anand Hariraj Udupa