Patents by Inventor Anand Hariraj Udupa

Anand Hariraj Udupa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7576668
    Abstract: A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: August 18, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Anand Hariraj Udupa, Vikas Kumar Sinha, Nitin Agarwal, Visvesvararaya A. Pentakota, Sandeep Oswal
  • Publication number: 20090184853
    Abstract: An aspect of the present invention avoids an amplifier of an analog to digital converter (ADC) from entering a saturation region. In an embodiment, a sample of an input signal to an ADC is compared with the upper and lower full-scale levels of the ADC. If input overload is detected, inputs to amplifiers in an input stage of the ADC are forced to zero for the duration of the input overload, and are thus prevented from going into saturation. Input overload conditions are signaled directly to an output digital block of the ADC, which provides output digital codes equivalent to either the upper or the lower full scale level depending on whether the input overload is signaled as exceeding the upper level or the lower level. Input overload recovery time of the ADC may thus be minimized.
    Type: Application
    Filed: December 18, 2008
    Publication date: July 23, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anand Hariraj Udupa, Neeraj Shrivastava, Nitin Agarwal
  • Patent number: 7310058
    Abstract: A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: December 18, 2007
    Assignee: Texas Instruments (India) Private Limited Texas Instruments Incorporated
    Inventors: Anand Hariraj Udupa, Vikas Kumar Sinha, Nitin Agarwal, Visvesvaraya A. Pentakota, Sandeep Oswal
  • Patent number: 7088149
    Abstract: Low voltage transistors are used in high voltage environment. The low voltage transistors may be used in the path of processing of a signal to increase the throughput performance. By using high voltage supply associated with the high voltage environment, a higher SNR may be attained. Various techniques are implemented to ensure that the low voltage transistors are not damaged by prolonged exposure to high voltages.
    Type: Grant
    Filed: November 29, 2003
    Date of Patent: August 8, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Anand Hariraj Udupa, Visvesvaraya A. Pentakota, Shakti Shankar Rath, Gautam Salil Nandi, Vineet Mishra, Ravishankar S. Ayyagari, Nitin Agarwal
  • Patent number: 6985006
    Abstract: The rate at which the output of an output buffer changes is determined, and the strength of the output buffer is modified until the rate of change reaches a desired rate. The desired rate may be selected such that strength of the output buffer matches the then existing load. In other words, the strength may be only as much as needed to drive the then existing load. As a result, effects such as switching noise may be considerably reduced.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: January 10, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Anand Hariraj Udupa, Visvesvaraya Pentakota Appala
  • Patent number: 6977547
    Abstract: A resistor (or a component with impedance that does not change) is provided across the output of an amplifier, which minimizes the changes in the amplification factor of an amplification circuit during operation.
    Type: Grant
    Filed: November 28, 2003
    Date of Patent: December 20, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Anand Hariraj Udupa, Visvesvaraya A. Pentakota
  • Publication number: 20040191976
    Abstract: The rate at which the output of an output buffer changes is determined, and the strength of the output buffer is modified until the rate of change reaches a desired rate. The desired rate may be selected such that strength of the output buffer matches the then existing load. In other words, the strength may be only as much as needed to drive the then existing load. As a result, effects such as switching noise may be considerably reduced.
    Type: Application
    Filed: March 27, 2003
    Publication date: September 30, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Anand Hariraj Udupa, Visvesvaraya Pentakota Appala
  • Patent number: 6694063
    Abstract: An offset is used to correct the output of a charge coupled device (CCD). The correction to the offset is determined by an exponential curve which allows for greater correction when error is large, and little correction when the error is small. The exponential curve may be viewed as a sequence of connected linear segments, and the correction to the offset may be determined by the slope of the segment to which the error maps. As the slopes at large errors are steep, the slope is correspondingly high, and the offset converges towards the correct value quickly. Power consumption is optimized by implementing the offset generation circuit using capacitor charge sharing principles.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: February 17, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Suhas R. Kulhalli, Supriyo Palit, Sindhuja Sridharan, Shakti Shankar Rath, Anand Hariraj Udupa
  • Publication number: 20020080406
    Abstract: An offset is used to correct the output of a charge coupled device (CCD). The correction to the offset is determined by an exponential curve which allows for greater correction when error is large, and little correction when the error is small. The exponential curve may be viewed as a sequence of connected linear segments, and the correction to the offset may be determined by the slope of the segment to which the error maps. As the slopes at large errors are steep, the slope is correspondingly high, and the offset converges towards the correct value quickly. Power consumption is optimized by implementing the offset generation circuit using capacitor charge sharing principles.
    Type: Application
    Filed: December 21, 2000
    Publication date: June 27, 2002
    Inventors: Suhas R. Kulhalli, Supriyo Palit, Sindhuja Sridharan, Shakti Shankar Rath, Anand Hariraj Udupa