Abstract: A system for testing substrates includes a first elongated member including an outer end, an inner end, an outer surface that extends between the outer and inner ends, and a concave surface at the inner end, and a second elongated member including an outer end, an inner end, an outer surface that extends between the outer and inner ends of the second elongated member, and a convex surface at the inner end of the second elongated member that opposes the concave surface at the inner end of the first elongated member. A joint interconnects the first and second elongated members for guiding sliding movement of the concave surface of the first elongated member over the convex surface of the second elongated member between extended and flexed positions. A first clamping assembly is coupled with the first elongated member and at least one first clamping assembly spring normally urges the first clamping assembly away from the inner end of the first elongated member.

Abstract: Compounds and compositions of matter are provided that are small molecule antimicrobials. The compounds are selected from JH-144, TH-04 or TH-08 or combinations thereof. Compositions of matter are provided which in an embodiment may comprise a carrier, and in further embodiments may comprise a pharmaceutically acceptable excipient, film, biofilm or edible film. Methods of use are provided in which the composition may be administered to a subject in need thereof, and in an embodiment where the subject has a bacterial infection. Other embodiments provide the composition may be contacted with surface to eliminate or reduce bacteria.

Abstract: An analog to digital converter (ADC) includes a conversion circuit digitizing an input analog signal to produce an output digital signal. A current generator generates a constant bias current. A current mirror circuit includes an input transistor receiving the constant bias current, an output transistor in a mirroring relationship with the input transistor and generating a variable bias current, and a parallel transistor circuit selectively coupling a parallel transistor in parallel with the input transistor or the output transistor in response to a control signal. The control signal is representative of the conversion rate of the ADC. A buffer generates a common mode voltage for use by the conversion circuit, from the variable bias current.

Abstract: In a particular implementation, an apparatus to control clamping devices includes a first control circuit and a second control circuit. The first control circuit is responsive to a detection signal and generates a first drive signal to control a body diode of a clamping device. The second control circuit is responsive to the detection signal and generates a second drive signal to control the gate terminal of the clamping device.

Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block.

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.

Abstract: Apparatuses for substrate transfer are provided. A lift pin assembly can include a lift pin, a purge cylinder, and a lift pin guide. The lift pin guide is disposed adjacent the purge cylinder. The lift pin guide and the purge cylinder have a passage formed therethough in which the lift pin is disposed. The purge cylinder includes one or more nozzles that direct the flow of gas radially inward into a portion of the passage disposed in the purge cylinder. The one or more nozzles are disposed radially outward from the lift pin. The purge cylinder reduces particle deposition on the substrate by preventing contact between the lift pin and the support assembly as the lift pin is in motion.

Abstract: Techniques for implementing a self-test procedure of an integrated circuit are provided, where the self-test procedure comprises testing for an electrical connection between first and second input-output pads of the integrated circuit. A control device is capable of adapting a functional configuration of usage of the first and second input-output pads in dependence on presence of the electrical connection. A corresponding integrated circuit, printed circuit and method are also provided. These techniques allow the integrated circuit to be used in a variety of contexts, without requiring physical customisation of the integrated circuit to adapt it to its usage context, in particular where connections from the context to the pads of the integrated circuit may be made to individual pads in some contexts or may span more than one pad in other contexts.

Abstract: Aspects of the present disclosure are directed to dynamically adjusting control plane policing throughput of low (or lower) priority control plane traffic to permit higher throughput. The drop rate for low or lower priority control plane traffic can be determined to be above a threshold value. The processor utilization can be determined to be operating under normal utilization (or at a utilization within a threshold utilization value). The control plane policing for control plane traffic for the low or lower class of service can be increased (or decreased) to permit lower class of service control traffic to be transmitted using higher class of service resources without adjusting the priority levels for the lower class of service control traffic.

Abstract: A method and a system of capturing an image of a card having a magnetic stripe is provided. The method includes obtaining a first image by an imaging device of the card, obtaining a plurality of images of the card via color delta analysis, and obtaining a third image of the card by comparing the first and the plurality of images.

Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block.

Abstract: The present disclosure provides an optical fibre. The optical fibre includes a glass core, a glass cladding, a primary coating layer, and a secondary coating layer. The glass cladding surrounds the glass core. In addition, the primary coating layer sandwiched between the glass cladding and the secondary coating layer. Further, the secondary coating layer surrounds the primary coating layer. The primary coating layer has diameter of up to is in the range of 130 to 155 micrometers. Furthermore, the secondary coating layer has diameter in a range of about 160 micrometers to 180 micrometers. Moreover, diameter of the optical fibre is about 190 micrometers.

Abstract: An automated computer operating software system for automatically generating user profiles is disclosed. The system is configured to automatically creates a profile or a number profiles based on biometric methods but also stores the profile(s) information along with an associated device(s) information and user generated data locally and remotely through various hardware modules and can also retrieve this information to any other device based on biometric authentication on the other device and auto adjust the operating parameters according to that other device and its operational parameters and again continue this same kind of auto creating, backing up and retrieving of both the profile of the user and device as well in a continuous loop of infinite number devices and user profiles.

Abstract: A dialogue intent analyzer uses a conversation between a user and agent, and intents in the conversation to predict a set of answers that better respond to pending user question. The dialogue intent analyzer understands the context surrounding the pending question by capturing and modeling prior conversation and intents within the conversation. Dialogue intent analyzer also reduces genericness in predicted answers by weighting previously used answers based on their frequency and length. Dialogue intent analyzer also increases diversity of predicted answers by using a diverse beam search.

Abstract: The present disclosure provides an optical fibre. The optical fibre includes a core region, a primary trench region and a secondary trench region. The core region has a radius r1. In addition, the core region has a relative refractive index ?1. Further, the primary trench region has a relative refractive index ?3. Furthermore, the primary trench region has a curve parameter ?trench-1. Moreover, the secondary trench region has a relative refractive index ?4. Also, the secondary trench region has a curve parameter ?trench-2.

Abstract: The present disclosure provides an optical fibre. The optical fibre includes a core extended from a central longitudinal axis to a first radius r1. Further, the optical fibre includes a first trench region extended from a second radius r2 to a third radius r3, a second trench region extended from the third radius r3 to a fourth radius r4 and a cladding region extended from the fourth radius r4 to a fifth radius r5.

Abstract: The present disclosure provides a universal optical fiber (100). The universal optical fiber (100) includes a core (102) extended from a central longitudinal axis (110) to a first radius r1. In addition, the universal optical fiber (100) includes a buffer clad (104) region extending from the first radius r1 to a second radius r2. Further, the universal optical fiber (100) includes a trench region (106) extending from the second radius r2 to a third radius r3. Furthermore, the universal optical fiber (100) includes a cladding (108) extending from the third radius to a fourth radius r4. Moreover, the core (102), the buffer clad region (104), the trench region (106) and the cladding (108) are concentrically arranged.

Abstract: Various implementations described herein are directed to multi-stage system. The system may include a first stage having a current bias generator that generates a biasing current. The system may include a second stage that is coupled to the first stage, and the second stage may include a load that utilizes the biasing current generated by the current bias generator.

Abstract: A circuit comprises a power controller, a real-time clock (RTC) sub-system, and a processing sub-system. The RTC sub-system includes an alarm register storing a predetermined time for a task, and provides an early warning countdown and a scheduled event signal. The processing sub-system includes a processor, a preemptive wakeup circuit, and a component coupled to the processor and configured to execute the task with the processor. The preemptive wakeup circuit comprises a selector logic circuit, a comparator, and a wakeup initiation circuit. The selector logic circuit receives latency values indicative of wakeup times for a clock generator and the component, and outputs a longest wakeup time to the comparator, which indicates when the early warning countdown and the longest wakeup time are equal. The wakeup initiation circuit generates a clock request and disables the sleep mode indicator. The power controller provides a clock signal and wakes the component.

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.