Abstract: Integrated circuit dies, systems, and techniques are described herein related to one transistor-one capacitor dynamic random access memory. A memory device includes vertically aligned transistors having annular semiconductor structures and a shared bit line extending through the annular semiconductor structures, and vertically aligned capacitors having annular first capacitor plates, annular capacitor dielectric structures, and a shared second capacitor plate extending through the annular first capacitor plates, such that the annular first capacitor plates are in contact with corresponding ones of the annular semiconductor structures.

Abstract: Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.

Abstract: Stacked static random-access memory (SRAM) circuits have doubled word length for a given SRAM cell area. An integrated circuit (IC) die includes stacked SRAM cells in vertically adjacent device layers with access transistors connected to a common wordline. The IC die with stacked SRAM cells having a common word line may be attached to a substrate and coupled to a power supply and, advantageously, to an active-cooling structure. SRAM cells may be formed in vertically adjacent layers of a substrate and electrically connected at their access transistor gate electrodes.

Abstract: Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

Abstract: Integrated circuit dies, systems, and techniques are described herein related to three-dimensional dynamic random access memory. A memory device includes vertically aligned semiconductor structures coupled to independent gate structures, corresponding vertically aligned capacitors each coupled to a corresponding one of the semiconductor structures, and a bit line contact extending vertically across a depth of the semiconductor structures and coupled to each of the semiconductor structures.

Abstract: Bits are stored in an array with multiple storage elements sharing a single access transistor and a storage line coupled to the transistor. A single common select transistor accesses information stored in an array of storage elements. Other arrays of storage elements on parallel storage lines can be coupled into a crosspoint array by source lines orthogonal to the storage lines. The storage elements may be non-volatile. In an integrated circuit system, the array may be coupled to a power supply and a cooling structure.

Abstract: In embodiments of the present disclosure, enhanced nanoribbons of GAA FETs are formed using a high-temperature diffusion process before the source/drain regions are formed. The diffusion process includes forming an additive material layer (e.g., comprising germanium) around crystalline nanoribbons (e.g., comprising purely or predominantly silicon), forming a capping layer around the additive material layer, diffusing the additive material into the crystalline nanoribbons (e.g., via heating), and removing the capping layer.

Abstract: Semiconductor devices and systems with self-aligned backside contacts, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a channel, a source and a drain, source and drain contacts, and a gate. The channel includes multiple channel structures arranged vertically and substantially in parallel. The source and the drain are at opposite ends of the channel. The source and drain contacts are coupled to the source and the drain, respectively. Moreover, one of the source contact or the drain contact is above the source or the drain and the other of the source contact or the drain contact is below the source or the drain. The gate is around the channel structures, where a portion of the gate below the channel structures is thicker than respective portions of the gate between the channel structures in cross-section view.

Abstract: Techniques are provided herein to form semiconductor devices having cells that include both forksheet devices and GAA devices to increase cell performance. The techniques can be used in any number of integrated circuit applications and are particularly useful with respect to logic and memory cells. The dielectric spine of the forksheet devices extends in a first direction across the cell and also acts as a gate cut between the GAA devices. Accordingly, forksheet devices are formed on one side of the cell while GAA devices are formed on the opposite side of the cell. Semiconductor material from the nanosheets and nanoribbons has a tapering width (along a second direction orthogonal to the first direction) within a transition zone between the different sides of the cell.

Abstract: Devices, transistor structures, systems, and techniques are described herein related to gate all around field effect transistors having a stack of nanoribbons (i.e., semiconductor structures) contacted by epitaxial source and drain structures at opposite ends of the nanoribbons. The transistors include a gate structure vertically between the nanoribbons. The nanoribbons are doped at their opposing ends and/or gaps are laterally between the gate structure and the source and drain structures.

Abstract: Integrated circuit (IC) devices having dielectric spacers between parallel channel structures (e.g., of nanoribbons, nanowires, etc.). A transistor structure may have first and second channel layers between source and drain bodies, a gate stack with a gate metal and gate dielectric between the channel layers, and a dielectric spacer between the channel layers and between the gate dielectric and one of the source and drain bodies. The dielectric spacer may have a significant (or minimal) curvature such that a width of the dielectric spacer between the channel layers is much greater (or not much greater) than widths of the dielectric spacer at the channel layers or than a minimum distance separating the gate metal between the channel layers from one of the source and drain bodies. An added or altered etch may remove sacrificial dummy gate material from between the channel layers and the gate side of the dielectric spacer.

Abstract: An integrated circuit (IC) device having complementary dielectric plugs separating gate electrodes. An IC device includes a first gate-cut plug of silicon and nitrogen between and in contact with two gate structures of transistors of a first conductivity type and a second gate-cut plug between and in contact with two gate structures of transistors of a second conductivity type, complementary to the first conductivity type, and the second gate-cut plug has within a liner of silicon and nitrogen either an airgap or a dielectric of silicon and oxygen. Pairs of gate structures of transistors having both of the first and second conductivity types are separated by first and second gate-cut plugs.

Abstract: An integrated circuit structure includes a first interconnect layer including a first dielectric material. The first dielectric material has a first recess therein, the first recess having a first opening. The integrated circuit structure further includes a second interconnect layer above the first interconnect layer. The second interconnect layer includes a second dielectric material that has a second recess therein. The second recess has a second opening. In an example, at least a portion of the first opening of the first recess abuts and overlaps with at least a portion of the second opening of the second recess. In an example, a continuous conformal layer is on walls of the first and second recesses, and a continuous body of conductive material is within the first and second recesses.

Abstract: Techniques are provided herein to form semiconductor devices having nanowires with an increased strain. A thin layer of silicon germanium or germanium tin can be deposited over one or more suspended nanoribbons. An anneal process may then be used to drive the silicon germanium or germanium tin throughout the one or more semiconductor nanoribbons, thus forming one or more nanoribbons with a changing material composition along the lengths of the one or more nanoribbons. In some examples, at least one of the one or more nanoribbons includes a first region at one end of the nanoribbon having substantially no germanium, a second region at the other end of the nanoribbon having substantially no germanium, and a third region between the first and second regions having a substantially uniform non-zero germanium concentration. The change in material composition along the length of the nanoribbon imparts a compressive strain.

Abstract: Integrated circuit dies, systems, and techniques, are described herein related to single conductivity type transistor circuits operable at low temperatures. A system includes a functional circuit block of an integrated circuit die having a number of non-planar transistors all of the same conductivity type. The system further includes cooling structure integral to the integrated circuit die, coupled to the integrated circuit die, or both. The cooling structure is operable to remove heat from the integrated circuit die to achieve an operating temperature at the desired low temperature.

Abstract: Integrated circuit dies, systems, and techniques are described related to multiple transistor epitaxial layer source and drain transistor circuits operable at low temperatures. A system includes an integrated circuit die having a number of transistors each having a crystalline channel structure, a first layer epitaxial to the channel structure, and a second layer epitaxial to the first layer. The system further includes a cooling structure integral to the integrated circuit die, coupled to the integrated circuit die, or both. The cooling structure is operable to remove heat from the integrated circuit die to achieve an operating temperature at the desired low temperature.

Abstract: Techniques and mechanisms for providing epitaxial structures of an integrated circuit (IC). In an embodiment, an IC comprises a separation layer, and first and second channel stack structures at opposite surfaces of the separation layer. A first source or drain (SD) structure extends to the first channel stack structure, and a second SD structure extends to the second channel stack structure. A hole extends through the separation layer, wherein the first and second SD structures are formed concurrently by a deposition of an epitaxial (epi) material from one side of the hole. An insulator material of the separation layer facilitates separation of the first and second SD structures from each other during the epi deposition. In another embodiment, respective crystal orientations in the first and second SD structures each face the same direction along a vertical dimension which is orthogonal to the surfaces of the separation layer.

Abstract: Techniques are provided herein to form semiconductor devices having strained channel regions. In an example, semiconductor nanoribbons of silicon germanium (SiGe) or germanium tin (GeSn) may be formed and subsequently annealed to drive the germanium or tin inwards along a portion of the semiconductor nanoribbons thus increasing the germanium or tin concentration through a central portion along the lengths of the one or more nanoribbons. Specifically, a nanoribbon may have a first region at one end of the nanoribbon having a first germanium concentration, a second region at the other end of the nanoribbon having substantially the same first germanium concentration (e.g., within 5%), and a third region between the first and second regions having a second germanium concentration higher than the first concentration. A similar material gradient may also be created using tin. The change in material composition (gradient) along the nanoribbon length imparts a compressive strain.

Abstract: Techniques are provided to form an integrated circuit having different semiconductor devices with different backside contact structures. Field effect transistors (FETs) each includes semiconductor material extending in a first direction between source and drain regions, and gate structures extending in a second direction around the semiconductor material of each FET. Different contact structures are formed on the source or drain regions of the n-channel FETs compared to the p-channel FETs. A backside contact structure on an n-channel source or drain region includes a first layer of phosphorous-doped titanium, a second layer that includes scandium, and a third layer that includes a metal, such as molybdenum. A backside contact structure on a p-channel source or drain region may include only a layer of metal, such as molybdenum, or the layer of metal and a layer of boron-doped titanium. The contact structures may be used to provide enhanced ohmic contact.

Abstract: Techniques are provided herein to form a semiconductor diode device within an integrated circuit. In an example, a diode device includes separate fins or bodies of semiconductor material that are separated by an insulating barrier. One of the fins or bodies is doped with n-type dopants while the other fin or body is doped with p-type dopants. Each of the first and second fins or bodies includes an epitaxially grown region over it that includes the corresponding dopant type with a higher dopant concentration. Additionally, each of the first and second fins or bodies includes another epitaxially grown region on the backside (e.g., under the fins or bodies) of the corresponding dopant type with a lower dopant concentration compared to the epitaxial regions on the opposite side of the fins or bodies. An undoped or lightly doped layer may also be formed between the epitaxially grown regions on the backside.