Abstract: The invention utilizes the linear complexity of orthogonal vectors to reduce the number of equations (or variables) to be solved. The present invention constructs a power model of a set of combinations of states without considering irrelevant combinations. The invention distinguishes between the switching direction on the input and the output pin. The invention considers state-dependency as a function of power consumed and depending on the paths through internal nodes. The model considers switching input pins that do not cause the output pin to switch to overcome inaccuracies caused by combining the power pin model with the state and arc power model with state. The model considers switching input pins that cause the output pin to switch. For cells in which the slewrate propagation effect from input to output is negligible, the invention uses a model of 2 power pins with state. The invention also determines the validity of this model.

Abstract: A method of creating models for power estimation of a circuit comprising generating an input space for the circuit. The input space is separated into multiple power modes corresponding to regions that display similar power behavior. Separate power models are generated for each of said multiple power modes. A power mode identification function is created that selects an appropriate power model from the separate power models based on the present and past values of the circuit inputs.

Abstract: A circuit comprising a plurality of components sharing at least one shared resource, and a lottery manager. The lottery manager is adapted to receive request for ownership for said at least one shared resource from a subset of the plurality of components. Each of the subset of the plurality of components are assigned lottery tickets. The lottery manager is adapted to probabilistically choose one component from the subset of the plurality of components for assigning said at least one shared resource. The probabilistic choosing is weighted based on a number of lottery tickets being assigned to each of the subset of the plurality of components.

Abstract: A method and apparatus for design-for-low-power of register transfer level (RTL) controller/data path circuits that implement control-flow intensive specifications. The method of the invention focuses on multiplexer networks and registers which dominate the total circuit power consumption and reduces generation and propagation of glitches in both the control and data path parts of the circuit. Further the method reduces glitching power consumption by minimizing propagation of glitches in the RTL circuit through restructuring multiplexer networks (to enhance data correlations and eliminate glitchy control signals), clocking control signals, and inserting selective rising/falling delays, in order to kill the propagation of glitches from control as well as data signals. To reduce power consumption in registers, the clock inputs to registers are gated with conditions derived by an analysis of the RTL circuit, ensuring that glitches are not introduced on the clock signals.

Abstract: A method for designing a circuit with reduced power consumption using a Common-Case Computation (CCC) based design. The method comprising identifying a set of common case computations from a schedule of the circuit, designing add on common detection circuit that detects the set of common case computations, designing add on common case execution circuit that executes the set of common case computations; and integrating the add on circuitry with the original circuit.

Abstract: This present invention presents a Common Case Computation (CCC) based design. A computation circuit with reduced power consumption, said computation circuit having a plurality of components. The components include a general purpose circuit, a common case detection circuit and a common case execution circuit. The common case detection circuit detects an occurrence of a common case based on a first subset of primary inputs and a first subset of internal variables for the general purpose circuit, and the common case execution circuit computes a subset of primary outputs of the general purpose circuit based on a second subset of primary inputs for the general purpose circuits and a second subset of internal variables for the general purpose circuit. The first subset of the primary inputs and the first subset of internal variables can be the same as the second subset of primary variables and the second subset of internal variables respectively.

Abstract: A power management method and system targeted toward high-level synthesis of data-dominated behavioral descriptions. The method of the present invention is founded on the observation that variable assignment can significantly affect power management opportunities in the synthesized architecture. Based on this observation, a procedure for constraining variable assignment is provided so that the functional units in the synthesized architecture do not execute any spurious operations.

Abstract: A complete procedure for verifying register-transfer logic against its scheduled behavior in a high-level synthesis environment is provided. A new method that is both complete and practical for verification is provided. Hardware verification is known to be a hard problem and the proposed verification technique leverages off the fact that high-level synthesis--performed manually or by means of high-level synthesis software--proceeds from the algorithmic description of the design to structural RTL through a sequence of very well defined steps, each limited in its scope. Equivalence checking task is partitioned into two simpler subtasks, verifying the validity of register sharing, and verifying correct synthesis of the RYL interconnect and control. While state space traversal is unavoidable for verifying validity of the register sharing, irrelevant portions of the design are automatically abstracted out, significantly simplifying the task that must be performed by a back-end model checker.

Abstract: A low-overhead controller-based power management technique that re-specifies control signals to reconfigure existing multiplexer networks and functional units to minimize unnecessary activity. Though the control signals in an RT-level implementation are fully specified, they can be re-specified under certain states/conditions when the data path components that they control need not be active. Another aspect of this invention is an algorithm to perform power management through controller re-specification, that consist of constructing an activity graph for each data path component, identifying conditions under which the component need not be active, and re-labeling the activity graph resulting in re-specification of the corresponding control expressions. The algorithm avoids the above negative effects of controller re-specification.

Abstract: A computer-aided design tool and associated methods address the problem of high-level behavioral synthesis, useful in the design of semiconductor integrated circuit for minimum power consumption. The tool makes a plurality of types of power reducing changes, and evaluates the results using iterative improvement. In a particular embodiment, "moves" corresponding to alterations of scheduling of operations or resource sharing are iteratively proposed and evaluated with a power "cost function" defined by summing estimates of the switched capacitance of each resource element. In an extension of that embodiment, moves corresponding to alterations of module selection and clock selection are also evaluated.

Abstract: A new dynamic process for test sequence compaction and test cycle reduction that identifies bottlenecks that prevent vector compaction and test cycle reduction for test sequences generated initially and generates subsequent test sequences with the aim of eliminating bottlenecks of the initially generated test sequences. To apply the process to sequential circuits, a sliding anchor frame technique is used that involves specifying the unspecified bits of a partially specified test sequence to detect other faults.