Patents by Inventor Anand Raghunathan

Anand Raghunathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966714
    Abstract: A circuit of cells used as a memory array and capable of in-memory arithmetic which includes a plurality of signed ternary processing, each signed ternary processing cell includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first signed ternary operand, a signed ternary input forming a second signed ternary operand, and a signed ternary output, wherein the signed ternary output represents a signed multiplication of the first signed ternary operand and the second signed ternary operand, a sense circuit adapted to output a subtraction result.
    Type: Grant
    Filed: January 30, 2022
    Date of Patent: April 23, 2024
    Assignee: Purdue Research Foundation
    Inventors: Shubham Jain, Anand Raghunathan, Sumeet Kumar Gupta
  • Publication number: 20240118892
    Abstract: Methods and apparatuses relating to processing neural networks are described. In one embodiment, an apparatus to process a neural network includes a plurality of fully connected layer chips coupled by an interconnect; a plurality of convolutional layer chips each coupled by an interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips including an interconnect to couple each of a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of a column of compute intensive tiles between a first memory intensive tile and a second memory intensive tile.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Inventors: Swagath VENKATARAMANI, Dipankar DAS, Ashish RANJAN, Subarno BANERJEE, Sasikanth AVANCHA, Ashok JAGANNATHAN, Ajaya V. DURG, Dheemanth NAGARAJ, Bharat KAUL, Anand RAGHUNATHAN
  • Patent number: 11681529
    Abstract: Systems, methods, and apparatuses relating to access synchronization in a shared memory are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, and an execution unit to execute the decoded instruction to: receive a first input operand of a memory address to be tracked and a second input operand of an allowed sequence of memory accesses to the memory address, and cause a block of a memory access that violates the allowed sequence of memory accesses to the memory address. In one embodiment, a circuit separate from the execution unit compares a memory address for a memory access request to one or more memory addresses in a tracking table, and blocks a memory access for the memory access request when a type of access violates a corresponding allowed sequence of memory accesses to the memory address for the memory access request.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: June 20, 2023
    Assignee: Intel Corporation
    Inventors: Swagath Venkataramani, Dipankar Das, Sasikanth Avancha, Ashish Ranjan, Subarno Banerjee, Bharat Kaul, Anand Raghunathan
  • Publication number: 20220241623
    Abstract: A respirator includes a mask shell, a face flange attached to a rear edge of the mask shell, a filter cover removably attachable to the mask shell, a filtration media removably secured between the filter cover and the mask shell, and scannable identification device.
    Type: Application
    Filed: February 2, 2022
    Publication date: August 4, 2022
    Applicant: AUSTIN BREATHE PROJECT, PBC
    Inventors: Kyle ELLISON, Michelle FRENCH, Shahram SHAFIE, Anand RAGHUNATHAN, Shahab SASSAN
  • Publication number: 20220206751
    Abstract: A circuit of cells used as a memory array and capable of in-memory arithmetic is disclosed which includes a plurality of signed ternary processing, each signed ternary processing cell includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first signed ternary operand, a signed ternary input forming a second signed ternary operand, and a signed ternary output, wherein the signed ternary output represents a signed multiplication of the first signed ternary operand and the second signed ternary operand, a sense circuit adapted to output a subtraction result.
    Type: Application
    Filed: January 30, 2022
    Publication date: June 30, 2022
    Applicant: Purdue Research Foundation
    Inventors: Shubham Jain, Anand Raghunathan, Sumeet Kumar Gupta
  • Patent number: 11281429
    Abstract: A ternary processing cell used as a memory cell and capable of in-memory arithmetic is disclosed which includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first ternary operand, a ternary input establishing a second ternary operand, and a ternary output, wherein the ternary output represents a multiplication of the first ternary operand and the second ternary operand.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: March 22, 2022
    Assignee: Purdue Research Foundation
    Inventors: Shubham Jain, Anand Raghunathan, Sumeet Kumar Gupta
  • Publication number: 20220050683
    Abstract: Methods and apparatuses relating to processing neural networks are described. In one embodiment, an apparatus to process a neural network includes a plurality of fully connected layer chips coupled by an interconnect; a plurality of convolutional layer chips each coupled by an interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips including an interconnect to couple each of a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of a column of compute intensive tiles between a first memory intensive tile and a second memory intensive tile.
    Type: Application
    Filed: October 26, 2021
    Publication date: February 17, 2022
    Inventors: Swagath VENKATARAMANI, Dipankar DAS, Ashish RANJAN, Subarno BANERJEE, Sasikanth AVANCHA, Ashok JAGANNATHAN, Ajaya V. DURG, Dheemanth NAGARAJ, Bharat KAUL, Anand RAGHUNATHAN
  • Publication number: 20210382719
    Abstract: Systems, methods, and apparatuses relating to access synchronization in a shared memory are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, and an execution unit to execute the decoded instruction to: receive a first input operand of a memory address to be tracked and a second input operand of an allowed sequence of memory accesses to the memory address, and cause a block of a memory access that violates the allowed sequence of memory accesses to the memory address. In one embodiment, a circuit separate from the execution unit compares a memory address for a memory access request to one or more memory addresses in a tracking table, and blocks a memory access for the memory access request when a type of access violates a corresponding allowed sequence of memory accesses to the memory address for the memory access request.
    Type: Application
    Filed: August 24, 2021
    Publication date: December 9, 2021
    Inventors: Swagath VENKATARAMANI, Dipankar DAS, Sasikanth AVANCHA, Ashish RANJAN, Subarno BANERJEE, Bharat KAUL, Anand RAGHUNATHAN
  • Patent number: 11151040
    Abstract: An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.
    Type: Grant
    Filed: March 24, 2019
    Date of Patent: October 19, 2021
    Assignee: Purdue Research Foundation
    Inventors: Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan
  • Patent number: 11106464
    Abstract: Systems, methods, and apparatuses relating to access synchronization in a shared memory are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, and an execution unit to execute the decoded instruction to: receive a first input operand of a memory address to be tracked and a second input operand of an allowed sequence of memory accesses to the memory address, and cause a block of a memory access that violates the allowed sequence of memory accesses to the memory address. In one embodiment, a circuit separate from the execution unit compares a memory address for a memory access request to one or more memory addresses in a tracking table, and blocks a memory access for the memory access request when a type of access violates a corresponding allowed sequence of memory accesses to the memory address for the memory access request.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Swagath Venkataramani, Dipankar Das, Sasikanth Avancha, Ashish Ranjan, Subarno Banerjee, Bharat Kaul, Anand Raghunathan
  • Publication number: 20210110581
    Abstract: A tomography system having a central processing unit, a system memory communicatively connected to the central processing unit, and a hardware acceleration unit communicatively connected to the central processing unit and the system memory, the hardware accelerator configured to perform at least a portion of an MBIR process on computer tomography data. The hardware accelerator unit may include one or more voxel evaluation modules which evaluate an updated value of a voxel given a voxel location in a reconstructed volume. By processing voxel data for voxels in a voxel neighborhood, processing time is reduces.
    Type: Application
    Filed: September 25, 2020
    Publication date: April 15, 2021
    Applicant: Purdue Research Foundation
    Inventors: Junshi Liu, Swagath Venkataramani, Singanallur V. Venkatakrishnan, Charles A. Bouman, Anand Raghunathan
  • Publication number: 20210089272
    Abstract: A ternary processing cell used as a memory cell and capable of in-memory arithmetic is disclosed which includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first ternary operand, a ternary input establishing a second ternary operand, and a ternary output, wherein the ternary output represents a multiplication of the first ternary operand and the second ternary operand.
    Type: Application
    Filed: September 25, 2019
    Publication date: March 25, 2021
    Applicant: Purdue Research Foundation
    Inventors: Shubham Jain, Anand Raghunathan, Sumeet Kumar Gupta
  • Patent number: 10722719
    Abstract: According to some embodiments, a system for securing communications between an implantable wearable medical device (IWMD) and an external device (ED) is disclosed. The system includes a wireless radio frequency (RF) channel configured for communication between the IWMD and the ED. The system further includes a vibration-based side channel configured for verifying communication between the IWMD and the ED such that the RF channel is activated only when the IWMD detects a vibration signal generated by an ED.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: July 28, 2020
    Assignee: THE TRUSTEES OF PRINCETON UNIVERSITY
    Inventors: Younghyun Kim, Woo Suk Lee, Vijay Raghunathan, Niraj K. Jha, Anand Raghunathan
  • Patent number: 10652237
    Abstract: A user authentication system for an electronic device for use with a plurality of wireless wearable medical sensors (WMSs) and a wireless base station that receives a biomedical data stream (biostream) from each WMS. The system includes a BioAura engine located on a server, the server has a wireless transmitter/receiver with receive buffers that store the plurality of biostreams, the BioAura engine has a look up stage and a classifier, the classifier generates an authentication output based on the plurality of biostreams, the authentication output authenticates the user's access to the electronic device. The wireless base station has a transmitter/receiver having receive buffers that store the biomedical data from each WMS, the wireless base station has a communication engine that retrieves the biostream from each WMS and transmits the plurality of biostreams to the server.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: May 12, 2020
    Assignees: THE TRUSTEES OF PRINCETON UNIVERSITY, INDIAN STATISTICAL INSTITUTE, PURDUE RESEARCH FOUNDATION
    Inventors: Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
  • Publication number: 20190303743
    Abstract: Methods and apparatuses relating to processing neural networks are described. In one embodiment, an apparatus to process a neural network includes a plurality of fully connected layer chips coupled by an interconnect; a plurality of convolutional layer chips each coupled by an interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips including an interconnect to couple each of a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of a column of compute intensive tiles between a first memory intensive tile and a second memory intensive tile.
    Type: Application
    Filed: September 27, 2016
    Publication date: October 3, 2019
    Inventors: Swagath VENKATARAMANI, Dipankar DAS, Ashish RANJAN, Subarno BANERJEE, Sasikanth AVANCHA, Ashok JAGANNATHAN, Ajaya V. DURG, Dheemanth NAGARAJ, Bharat KAUL, Anand RAGHUNATHAN
  • Publication number: 20190251712
    Abstract: A tomography system having a central processing unit, a system memory communicatively connected to the central processing unit, and a hardware acceleration unit communicatively connected to the central processing unit and the system memory, the hardware accelerator configured to perform at least a portion of an MBIR process on computer tomography data. The hardware accelerator unit may include one or more voxel evaluation modules which evaluate an updated value of a voxel given a voxel location in a reconstructed volume. By processing voxel data for voxels in a voxel neighborhood, processing time is reduces.
    Type: Application
    Filed: December 26, 2018
    Publication date: August 15, 2019
    Applicant: Purdue Research Foundation
    Inventors: Junshi Liu, Swagath Venkataramani, Singanallur V. Venkatakrishnan, Charles A. Bouman, Anand Raghunathan
  • Publication number: 20190243651
    Abstract: Systems, methods, and apparatuses relating to access synchronization in a shared memory are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, and an execution unit to execute the decoded instruction to: receive a first input operand of a memory address to be tracked and a second input operand of an allowed sequence of memory accesses to the memory address, and cause a block of a memory access that violates the allowed sequence of memory accesses to the memory address. In one embodiment, a circuit separate from the execution unit compares a memory address for a memory access request to one or more memory addresses in a tracking table, and blocks a memory access for the memory access request when a type of access violates a corresponding allowed sequence of memory accesses to the memory address for the memory access request.
    Type: Application
    Filed: September 27, 2016
    Publication date: August 8, 2019
    Applicant: Intel Corporation
    Inventors: Swagath VENKATARAMANI, Dipankar DAS, Sasikanth AVANCHA, Ashish RANJAN, Subarno BANERJEE, Bharat KAUL, Anand RAGHUNATHAN
  • Publication number: 20190220412
    Abstract: An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.
    Type: Application
    Filed: March 24, 2019
    Publication date: July 18, 2019
    Applicant: Purdue Research Foundation
    Inventors: Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan
  • Patent number: 10255186
    Abstract: An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: April 9, 2019
    Assignee: Purdue Research Foundation
    Inventors: Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan
  • Patent number: 10163232
    Abstract: A tomography system having a central processing unit, a system memory communicatively connected to the central processing unit, and a hardware acceleration unit communicatively connected to the central processing unit and the system memory, the hardware accelerator configured to perform at least a portion of an MBIR process on computer tomography data. The hardware accelerator unit may include one or more voxel evaluation modules which evaluate an updated value of a voxel given a voxel location in a reconstructed volume. By processing voxel data for voxels in a voxel neighborhood, processing time is reduces.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: December 25, 2018
    Assignee: PURDUE RESEARCH FOUNDATION
    Inventors: Junshi Liu, Swagath Venkataramani, Singanallur V. Venkatakrishnan, Charles A. Bouman, Anand Raghunathan