Patents by Inventor Anand S. Murthy
Anand S. Murthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12294027Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.Type: GrantFiled: January 8, 2024Date of Patent: May 6, 2025Assignee: Intel CorporationInventors: Anand S. Murthy, Daniel Boune Aubertine, Tahir Ghani, Abhijit Jayant Pethe
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Publication number: 20250142948Abstract: An IC device with one or more transistors may also include one or more vias and jumpers for delivering power to the transistors. For instance, a via may be coupled to a power plane. A jumper may be connected to the via and an electrode of a transistor. With the via and jumper, an electrical connection is built between the power plane and the electrode. The via may be self-aligned. The IC device may include a dielectric structure at a first side of the via. A portion of the jumper may be at a second side of the via. The second side opposes the first side. The dielectric structure and the portion of the jumper may be over another dielectric structure that has a different dielectric material from the dielectric structure. The via may be insulated from another electrode of the transistor, which may be coupled to a ground plane.Type: ApplicationFiled: October 31, 2023Publication date: May 1, 2025Applicant: Intel CorporationInventors: Robin Chao, Chiao-Ti Huang, Guowei Xu, Yang Zhang, Ting-Hsiang Hung, Tao Chu, Feng Zhang, Chia-Ching Lin, Anand S. Murthy, Conor P. Puls, Kan Zhang
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Publication number: 20250142870Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.Type: ApplicationFiled: December 27, 2024Publication date: May 1, 2025Inventors: Cory BOMBERGER, Anand S. MURTHY, Tahir GHANI, Anupama BOWONDER
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Patent number: 12288803Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).Type: GrantFiled: December 14, 2023Date of Patent: April 29, 2025Assignee: Intel CorporationInventors: Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani, Gilbert Dewey
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Patent number: 12288808Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.Type: GrantFiled: September 20, 2023Date of Patent: April 29, 2025Assignee: Intel CorporationInventors: Ryan Keech, Anand S. Murthy, Nicholas G. Minutillo, Suresh Vishwanath, Mohammad Hasan, Biswajeet Guha, Subrina Rafique
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Publication number: 20250113595Abstract: Multiple voltage threshold integrated circuit structures with local layout effect tuning, and methods of fabricating multiple voltage threshold integrated circuit structures with local layout effect tuning, are described. For example, an integrated circuit structure includes a first fin structure or vertical arrangement of horizontal nanowires. A second fin structure or vertical arrangement of horizontal nanowires is laterally spaced apart from the first fin structure or vertical arrangement of horizontal nanowires. An N-type gate structure is over the first fin structure or vertical arrangement of horizontal nanowires. A P-type gate structure is over the second fin structure or vertical arrangement of horizontal nanowires, the P-type gate structure in contact with the N-type gate structure with a PN boundary between the P-type gate structure and the N-type gate structure.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Inventors: Tao CHU, Minwoo JANG, Yanbin LUO, Paul PACKAN, Guowei XU, Chiao-Ti HUANG, Robin CHAO, Feng ZHANG, Ting-Hsiang HUNG, Chia-Ching LIN, Yang ZHANG, Chung-Hsun LIN, Anand S. MURTHY
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Publication number: 20250112120Abstract: Integrated circuit structures having deep via bar width tuning are described. For example, an integrated circuit structure includes a plurality of gate lines extending over first and second semiconductor nanowire stack channel structures or fin structures. A plurality of trench contacts is intervening with the plurality of gate lines. A conductive structure is between the first and second semiconductor nanowire stack channel structures or fin structures, the conductive structure having a first width in a first region and a second width in a second region between the first and second semiconductor nanowire stack channel structures or fin structures, the second width different than the first width.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Tao CHU, Minwoo JANG, Yanbin LUO, Paul PACKAN, Conor P. PULS, Guowei XU, Chiao-Ti HUANG, Robin CHAO, Feng ZHANG, Ting-Hsiang HUNG, Chia-Ching LIN, Yang ZHANG, Chung-Hsun LIN, Anand S. MURTHY
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Publication number: 20250113559Abstract: Trench contact structures with etch stop layers, and methods of fabricating trench contact structures with etch-stop layers, are described. In an example, an integrated circuit structure includes a fin structure. An epitaxial source or drain structure is on the fin structure. An isolation structure is laterally adjacent to sides of the fin structure. A dielectric layer is on at least a portion of a top surface of the isolation structure and partially surrounds the epitaxial source or drain structure and leaves an exposed portion of the epitaxial source or drain structure. A conductive trench contact structure is on the exposed portion of the epitaxial source or drain structure. The conductive trench contact structure does not extend into the isolation structure.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Inventors: Guowei XU, Chiao-Ti HUANG, Feng ZHANG, Robin CHAO, Tao CHU, Anand S. MURTHY, Ting-Hsiang HUNG, Chung-Hsun LIN, Oleg GOLONZKA, Yang ZHANG, Chia-Ching LIN
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Publication number: 20250107108Abstract: An IC device may include memory layers bonded to a logic layer with inclination. An angle between a memory layer and the logic layer may be in a range from approximately 0 to approximately 90 degrees. The memory layers may be over the logic layer. The IC device may include one or more additional logic layers that are parallel to a memory layer or perpendicular to a memory layer. The one or more additional logic layers may be over the logic layer. A memory layer may include memory cells. The logic layer may include logic circuits (e.g., sense amplifier, word line driver, etc.) that control the memory cells. Bit lines (or word lines) in different memory layers may be coupled to each other. A bit line and a word line in a memory layer may be controlled by logic circuits in different logic layers.Type: ApplicationFiled: September 25, 2023Publication date: March 27, 2025Applicant: Intel CorporationInventors: Abhishek A. Sharma, Sagar Suthram, Wilfred Gomes, Tahir Ghani, Anand S. Murthy, Pushkar Sharad Ranade
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Publication number: 20250104760Abstract: An IC device may include memory layers over a logic layer. A memory layer includes memory arrays, each of which includes memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. Bit lines of different memory arrays may be coupled using one or more vias or source/drain electrodes of transistors in the memory arrays. Alternatively, word lines of different memory arrays may be coupled using one or more vias or gate electrodes of transistors in the memory arrays. The logic layer has a logic circuit that can control data read operations and data write operations of the memory layers. The logic layer may include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the memory device.Type: ApplicationFiled: September 21, 2023Publication date: March 27, 2025Applicant: Intel CorporationInventors: Abhishek A. Sharma, Sagar Suthram, Wilfred Gomes, Anand S. Murthy, Tahir Ghani, Pushkar Sharad Ranade
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Publication number: 20250107175Abstract: Integrated circuit structures having reduced local layout effects, and methods of fabricating integrated circuit structures having reduced local layout effects, are described. For example, an integrated circuit structure includes an NMOS region including a first plurality of fin structures or vertical stacks of horizontal nanowires, and first alternating gate lines and trench contact structures over the first plurality of fin structures or vertical stacks of horizontal nanowires. The integrated circuit structure also includes a PMOS region including a second plurality of fin structures or vertical stacks of horizontal nanowires, and second alternating gate and trench contact structures over the second plurality of fin structures or vertical stacks of horizontal nanowires. A gate line is shared between the NMOS region and the PMOS region, and a trench contact structure is shared between the NMOS region and the PMOS region.Type: ApplicationFiled: September 25, 2023Publication date: March 27, 2025Inventors: Tao CHU, Minwoo JANG, Yanbin LUO, Paul PACKAN, Guowei XU, Chiao-Ti HUANG, Robin CHAO, Feng ZHANG, Ting-Hsiang HUNG, Chia-Ching LIN, Yang ZHANG, Chung-Hsun LIN, Anand S. MURTHY
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Publication number: 20250107107Abstract: An IC device may include memory layers over a logic layer. A memory layer may include memory arrays and one or more peripheral circuits coupled to the memory arrays. A memory array may include memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. The logic layer includes one or more logic circuits that can control data read operations and data write operations of the memory layers. The logic layer may also include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the IC device. The IC device may further include vias that couple the memory layers to the logic layer. Each via may be connected to one or more memory layers and the logic layer.Type: ApplicationFiled: September 21, 2023Publication date: March 27, 2025Applicant: Intel CorporationInventors: Abhishek A. Sharma, Sagar Suthram, Wilfred Gomes, Pushkar Sharad Ranade, Anand S. Murthy, Tahir Ghani
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Publication number: 20250095693Abstract: An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits, which may include MOSFET transistors. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. The logic circuits may include word line drivers and sense amplifiers. Word lines in different memory layers may share the same word line driver. Bit lines in different memory layers may share the same sense amplifier. The IC device may include front-back word line drivers, near-far sense amplifiers, near-far word line drivers, or front-back sense amplifiers. A memory layer may be bonded with the CMOS layer through a bonding layer that provides a bonding interface between the memory layer and the CMOS layer.Type: ApplicationFiled: September 15, 2023Publication date: March 20, 2025Applicant: Intel CorporationInventors: Abhishek A. Sharma, Juan G. Alzate-Vinasco, Fatih Hamzaoglu, Wilfred Gomes, Anand S. Murthy, Tahir Ghani, Van H. Le
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Publication number: 20250098260Abstract: Integrated circuit structures having patch spacers, and methods of fabricating integrated circuit structures having patch spacers, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. An internal gate spacer is between vertically adjacent ones of the stack of horizontal nanowires and laterally adjacent to the gate structure. An external gate spacer is along sides of the gate structure and over the stack of horizontal nanowires, the external gate spacer having one or more patch spacers therein.Type: ApplicationFiled: September 19, 2023Publication date: March 20, 2025Inventors: Guowei XU, Feng ZHANG, Chiao-Ti HUANG, Robin CHAO, Tao CHU, Chung-Hsun LIN, Oleg GOLONZKA, Yang ZHANG, Ting-Hsiang HUNG, Chia-Ching LIN, Anand S. MURTHY
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Publication number: 20250098179Abstract: An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits with MOSFET transistors. The CMOS layer may also include memory cells, e.g., SRAM cells. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. A logic circuit in the CMOS layer may control access to the memory cells. A memory layer may be bonded with the CMOS layer through a bonding layer that includes conductive structures coupled to a logic circuit in the CMOS layer or to bit lines or word lines in the memory layer. An additional conductive structure may be at the backside of a MOSFET transistor in the CMOS layer and coupled to a conductive structure in the bonding layer.Type: ApplicationFiled: September 15, 2023Publication date: March 20, 2025Inventors: Abhishek A. Sharma, Van H. Le, Fatih Hamzaoglu, Juan G. Alzate-Vinasco, Nikhil Jasvant Mehta, Vinaykumar Hadagali, Yu-Wen Huang, Honore Djieutedjeu, Tahir Ghani, Timothy Jen, Shailesh Kumar Madisetti, Jisoo Kim, Wilfred Gomes, Kamal Baloch, Vamsi Evani, Christopher Wiegand, James Pellegren, Sagar Suthram, Christopher M. Pelto, Gwang Soo Kim, Babita Dhayal, Prashant Majhi, Anand Iyer, Anand S. Murthy, Pushkar Sharad Ranade, Pooya Tadayon, Nitin A. Deshpande
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Patent number: 12237420Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.Type: GrantFiled: April 23, 2024Date of Patent: February 25, 2025Assignee: Intel CorporationInventors: Cory Bomberger, Anand S. Murthy, Tahir Ghani, Anupama Bowonder
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Publication number: 20250022878Abstract: Methods for fabricating a transistor arrangement of an IC structure by using a placeholder for backside contact formation, as well as related semiconductor devices, are disclosed. An example method includes forming, in a support structure (e.g., a substrate, a chip, or a wafer), a dielectric placeholder for a backside contact as the first step in the method. A nanosheet superlattice is then grown laterally over the dielectric placeholder, and a stack of nanoribbons is formed based on the superlattice. The nanoribbons are processed to form S/D regions and gate stacks for future transistors. The dielectric placeholder remains in place until the support structure is transferred to a carrier wafer, at which point the dielectric placeholder is replaced with the backside contact. Use of a placeholder for backside contact formation allows alignment of contact from the backside to appropriate device ports of a transistor arrangement.Type: ApplicationFiled: October 1, 2024Publication date: January 16, 2025Applicant: Intel CorporationInventors: Andy Chih-Hung Wei, Anand S. Murthy, Mauro J. Kobrinsky, Guillaume Bouche
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Publication number: 20250008723Abstract: Integrated circuit (IC) devices implementing three-dimensional (3D) floating body memory are disclosed. An example IC device includes a floating body memory cell comprising a transistor having a first source or drain (S/D) region, a second S/D region, and a gate over a channel portion between the first and second S/D regions; a BL coupled to the first S/D region and parallel to a first axis of a Cartesian coordinate system; a SL coupled to the second S/D region and parallel to a second axis of the coordinate system; and a WL coupled to or being a part of the gate and parallel to a third axis of the coordinate system. IC devices implementing 3D floating body memory as described herein may be used to address the scaling challenges of conventional memory technologies and enable high-density embedded memory compatible with advanced CMOS processes.Type: ApplicationFiled: June 27, 2023Publication date: January 2, 2025Applicant: Intel CorporationInventors: Abhishek A. Sharma, Wilfred Gomes, Tahir Ghani, Anand S. Murthy, Sagar Suthram
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Publication number: 20240431117Abstract: IC devices implementing memory with one access transistor coupled to multiple capacitors are disclosed. An example IC device includes a support structure (e.g., a substrate), an access transistor over the support structure, the access transistor having a region that is either a source region or a drain region, and a plurality of capacitors where at least two or more of the capacitors are in different layers above the access transistor. First capacitor electrodes of the plurality of capacitors are coupled to the region, and second capacitor electrodes of the plurality of capacitors are coupled to respective electrically conductive lines. IC devices implementing memory with one access transistor coupled to multiple capacitors as described herein may be used to address the scaling challenges of conventional 1T-1C memory technology and enable high-density embedded memory compatible with advanced CMOS processes.Type: ApplicationFiled: June 21, 2023Publication date: December 26, 2024Applicant: Intel CorporationInventors: Abhishek A. Sharma, Wilfred Gomes, Tahir Ghani, Anand S. Murthy
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Publication number: 20240431092Abstract: A transistor may include a source region, a drain region, a channel region between the source region and the drain region in a first direction, a gate electrode, a source contact, and a drain contact. A first portion of the gate electrode is over the channel region in a second direction substantially perpendicular to the first direction. A second portion of the gate electrode is over a first portion of the drain region in the second direction. The source contact is over at least part of the source region. The drain contact is over a second portion of the drain region. A distance from an edge of the first portion of the drain region to an edge of the gate electrode or to an edge the first trench electrode in the first direction is greater than a fourth of a length of the gate electrode in the first direction.Type: ApplicationFiled: June 21, 2023Publication date: December 26, 2024Applicant: Intel CorporationInventors: Abhishek A. Sharma, Wilfred Gomes, Tahir Ghani, Anand S. Murthy