Patents by Inventor Anand S. Murthy

Anand S. Murthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11121030
    Abstract: Techniques are disclosed for forming transistors employing a carbon-based etch stop layer (ESL) for preserving source and drain (S/D) material during contact trench etch processing. As can be understood based on this disclosure, carbon-based layers can provide increased resistance for etch processing, such that employing a carbon-based ESL on S/D material can preserve that S/D material during contact trench etch processing. This is due to carbon-based layers being able to provide more robust (e.g., more selective) etch selectivity during contact trench etch processing than the S/D material it is preserving (e.g., Si, SiGe, Ge, group III-V semiconductor material) and other etch stop layers (e.g., insulator material-based etch stop layers). Employing a carbon-based ESL enables a given S/D region to protrude from shallow trench isolation (STI) material prior to contact metal deposition, thereby providing more surface area for making contact to the given S/D region, which improves transistor performance.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: September 14, 2021
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Benjamin Chu-Kung, Seung Hoon Sung, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 11107890
    Abstract: An apparatus is described. The apparatus includes a FINFET device having a channel. The channel is composed of a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel. The subfin structure is composed of a second semiconductor material that is different than the first semiconductor material. The subfin structure is epitaxially grown on a substrate composed of a third semiconductor material that is different than the first and second semiconductor materials. The subfin structure has a doped region to substantially impede leakage currents between the channel and the substrate.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Matthew V. Metz, Willy Rachmady, Anand S. Murthy, Chandra S. Mohapatra, Tahir Ghani, Sean T. Ma, Jack T. Kavalieros
  • Patent number: 11101268
    Abstract: Techniques are disclosed for forming transistors employing non-selective deposition of source and drain (S/D) material. Non-selectively depositing S/D material provides a multitude of benefits over only selectively depositing the S/D material, such as being able to attain relatively higher dopant activation, steeper dopant profiles, and better channel strain, for example.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Scott J. Maddox, Ritesh Jhaveri, Pratik A. Patel, Szuya S. Liao, Anand S. Murthy, Tahir Ghani
  • Patent number: 11101356
    Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent insulator regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, a dopant-rich insulator cap is deposited adjacent to the source and/or drain regions, to provide dopant diffusion reduction. In some embodiments, the dopant-rich insulator cap is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10% by atomic percentage. In some embodiments, the dopant-rich insulator cap may have a thickness in the range of 10 to 100 nanometers and a height in the range of 10 to 200 nanometers.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Cory C. Bomberger, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung, Seung Hoon Sung, Siddharth Chouksey
  • Patent number: 11101350
    Abstract: Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements. The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (e.g., B, P, or As) into the adjacent Ge-rich channel region. In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon. Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion. In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region. Numerous embodiments, configurations, and variations will be apparent.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Benjamin Chu-Kung, Seung Hoon Sung, Jack T. Kavalieros, Tahir Ghani, Harold W. Kennel
  • Patent number: 11094785
    Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Glenn A. Glass, Anand S. Murthy, Tahir Ghani, Aravind S. Killampalli, Mark R. Brazier, Jaya P. Gupta
  • Patent number: 11081570
    Abstract: Integrated circuit transistor structures are disclosed that include a gate structure that is lattice matched to the underlying channel. In particular, the gate dielectric is lattice matched to the underlying semiconductor channel material, and in some embodiments, so is the gate electrode. In an example embodiment, single crystal semiconductor channel material and single crystal gate dielectric material that are sufficiently lattice matched to each other are epitaxially deposited. In some cases, the gate electrode material may also be a single crystal material that is lattice matched to the semiconductor channel material, thereby allowing the gate electrode to impart strain on the channel via the also lattice matched gate dielectric. A gate dielectric material that is lattice matched to the channel material can be used to reduce interface trap density (Dit). The techniques can be used in both planar and non-planar (e.g., finFET and nanowire) metal oxide semiconductor (MOS) transistor architectures.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Glenn A. Glass, Anand S. Murthy, Jack T. Kavalieros, Seung Hoon Sung, Benjamin Chu-Kung, Tahir Ghani
  • Patent number: 11069795
    Abstract: Integrated circuits include fins including an upper/channel region and a lower/sub-channel region, the lower region having a first chemical composition and opposing sidewalls adjacent to an insulator material, and the upper region having a second chemical composition. A first width indicates the distance between the opposing sidewalls of the lower region at a first location is at least 1 nm wider than a second width indicating the distance between the opposing sidewalls of the upper region at a second location, the first location being within 10 nm of the second location (or otherwise relatively close to one another). The first chemical composition is distinct from the second chemical composition and includes a surface chemical composition at an outer surface of the opposing sidewalls of the lower region and a bulk chemical composition therebetween, the surface chemical composition including one or more of oxygen, nitrogen, carbon, chlorine, fluorine, and sulfur.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Glenn A. Glass, Anand S. Murthy, Jun Sung Kang, Bruce E. Beattie, Anupama Bowonder, Biswajeet Guha, Ju H. Nam, Tahir Ghani
  • Patent number: 11056592
    Abstract: An integrated circuit (IC) includes a substrate that includes silicon. A first layer is on the substrate and includes a first monocrystalline semiconductor material, the first layer having a plurality of defects. A second layer is on the first layer and includes a second monocrystalline semiconductor material that includes germanium. A strained channel structure is above the first layer. A gate structure is at least above the channel structure. A source region is adjacent the channel structure. A drain region is adjacent the channel structure, such that the channel structure is laterally between the source region and the drain region.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Cory C. Bomberger, Glenn A. Glass, Anand S. Murthy, Ju H. Nam, Tahir Ghani
  • Patent number: 11049773
    Abstract: A transistor device comprising a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel comprises a channel material that is separated from a body of the same material on a substrate. A method comprising forming a trench in a dielectric layer on an integrated circuit substrate, the trench comprising dimensions for a transistor body including a width; depositing a spacer layer in a portion of the trench, the spacer layer narrowing the width of the trench; forming a channel material in the trench through the spacer layer; recessing the dielectric layer to define a first portion of the channel material exposed and a second portion of the channel material in the trench; and separating the first portion of the channel material from the second portion of the channel material.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Matthew V. Metz, Sean T. Ma, Cheng-Ying Huang, Tahir Ghani, Anand S. Murthy, Harold W. Kennel, Nicholas G. Minutillo, Jack T. Kavalieros, Willy Rachmady
  • Publication number: 20210167210
    Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Cory BOMBERGER, Anand S. MURTHY, Tahir GHANI, Anupama BOWONDER
  • Patent number: 11024737
    Abstract: A replacement fin layer is deposited on a sub-fin layer in trenches isolated by an insulating layer on a substrate. The replacement fin layer has first component rich side portions and a second component rich core portion. The second component rich core portion is etched to generate a double fin structure comprising the first component rich fins.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Chandra S. Mohapatra, Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan
  • Patent number: 11024713
    Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a drain region of doped semiconductor material on the substrate adjacent a second side of the semiconductor region, and a transition region in the drain region, adjacent the semiconductor region, wherein the transition region comprises varying dopant concentrations that increase in a direction away from the semiconductor region. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Dipanjan Basu, Glenn A. Glass, Harold W. Kennel, Ashish Agrawal, Benjamin Chu-Kung, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani
  • Publication number: 20210159339
    Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.
    Type: Application
    Filed: January 28, 2021
    Publication date: May 27, 2021
    Inventors: Anand S. MURTHY, Daniel Bourne AUBERTINE, Tahir GHANI, Abhijit Jayant PETHE
  • Patent number: 11011620
    Abstract: Techniques are disclosed for forming increasing channel region tensile strain in n-MOS devices. In some cases, increased channel region tensile strain can be achieved via S/D material engineering that deliberately introduces dislocations in one or both of the S/D regions to produce tensile strain in the adjacent channel region. In some such cases, the S/D material engineering to create desired dislocations may include using a lattice mismatched epitaxial S/D film adjacent to the channel region. Numerous material schemes for achieving multiple dislocations in one or both S/D regions will be apparent in light of this disclosure. In some cases, a cap layer can be formed on an S/D region to reduce contact resistance, such that the cap layer is an intervening layer between the S/D region and S/D contact. The cap layer includes different material than the underlying S/D region and/or a higher dopant concentration to reduce contact resistance.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Cory E. Weber, Anand S. Murthy, Karthik Jambunathan, Glenn A. Glass, Jiong Zhang, Ritesh Jhaveri, Szuya S. Liao
  • Patent number: 11004954
    Abstract: Integrated circuit transistor structures are disclosed that include a single crystal buffer structure that is lattice matched to the underlying single crystal silicon substrate. The buffer structure may be used to reduce sub-fin leakage in non-planar transistors, but can also be used in planar configurations. In some embodiments, the buffer structure is a single continuous layer of high bandgap dielectric material that is lattice matched to silicon. The techniques below can be utilized on NMOS and PMOS transistors, including any number of group IV and III-V semiconductor channel materials.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Glenn A. Glass, Anand S. Murthy, Jack T. Kavalieros, Seung Hoon Sung, Benjamin Chu-Kung, Tahir Ghani
  • Patent number: 10998270
    Abstract: Techniques are disclosed for forming transistor devices having reduced interfacial resistance in a local interconnect. The local interconnect can be a material having similar composition to that of the source/drain material. That composition can be a metal alloy of a group IV element such as nickel germanide. The local interconnect of the semiconductor integrated circuit can function in the absence of barrier and liner layers. The devices can be used on MOS transistors including PMOS transistors.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Glenn A. Glass, Van H. Le, Ashish Agrawal, Benjamin Chu-Kung, Anand S. Murthy, Jack T. Kavalieros
  • Patent number: 10985263
    Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a cap region on the substrate adjacent a second side of the semiconductor region, wherein the cap region comprises semiconductor material of a higher band gap than the semiconductor region, and a drain region comprising doped semiconductor material on the cap region. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Dipanjan Basu, Ashish Agrawal, Van H. Le, Benjamin Chu-Kung, Harold W. Kennel, Glenn A. Glass, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 10978568
    Abstract: Techniques are disclosed for passivation of transistor channel region interfaces. In some cases, the transistor channel region interfaces to be passivated include the interface between the semiconductor channel and the gate dielectric and/or the interface between the sub-channel semiconductor material and isolation material. For example, an aluminum oxide (also referred to as alumina) layer may be used to passivate channel/gate interfaces where the channel material includes silicon germanium, germanium, or a III-V material. The techniques can be used to reduce the interface trap density at the channel/gate interface and the techniques can also be used to passivate the channel/gate interface in both gate first and gate last process flows. The techniques may also include an additional passivation layer at the sub-channel/isolation interface to, for example, avoid incurring additional parasitic capacitance penalty.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Mark R. Brazier, Anand S. Murthy, Tahir Ghani, Owen Y. Loh
  • Publication number: 20210091181
    Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 25, 2021
    Inventors: Ryan KEECH, Anand S. MURTHY, Nicholas G. MINUTILLO, Suresh VISHWANATH, Mohammad HASAN, Biswajeet GUHA, Subrina RAFIQUE