Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: Techniques and mechanisms to impose stress on a transistor which includes a channel region and a source or drain region each in a fin structure. In an embodiment, a gate structure of the transistor extends over the fin structure, wherein a first spacer portion is at a sidewall of the gate structure and a second spacer portion adjoins the first spacer portion. Either or both of two features are present at or under respective bottom edges of the spacer portions. One of the features includes a line of discontinuity on the fin structure. The other feature includes a concentration of a dopant in the second spacer portion being greater than a concentration of the dopant in the source or drain region. In another embodiment, the fin structure is disposed on a buffer layer, wherein stress on the channel region is imposed at least in part with the buffer layer.

Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include a metal-all-around contact structure coupled with an S/D region are described herein. In one example, an IC structure may include a region of a doped semiconductor material. An IC structure may include a stack of nanoribbons of a semiconductor material including first portions and second portions on either side of the region, wherein the first portions are in contact with a first side of the region and the second portions are in contact with a second side of the region. An IC structure may include a conductive material over portions of the region between the first side and the second side in a same layer as at least one of the nanoribbons of the stack.

Abstract: An IC device may have active regions and one or more isolation regions. The IC device includes gates that are in parallel. One or more semiconductor structures (e.g., fins, nanoribbons, etc.) may extend across each gate in the IC device. Some of the gates are in the active regions. The other gates are in the isolation region. A gate in an active region may be between semiconductor regions, which may function as the source region and drain region of a transistor. A gate in an isolation region may be between insulator regions. The insulator regions may be formed from the backside of the IC device. For instance, semiconductor regions may be formed in both the active regions and the isolation regions. The semiconductor regions in the regions designated to be isolation regions may be removed from the backside and filled with one or more electrical insulators.

Abstract: Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.

Abstract: An IC device may have activation regions and an isolation region between the active regions. An active region may include one or more transistors. The IC device includes gates that are in parallel. Some of the gates are in the active regions. The other gates are in the isolation region. A source or drain region may be formed between a gate in the isolation region and a gate in a transistor in the first direction. The IC device may include one or more semiconductor structures that extend across a gate in a transistor, and the semiconductor structures may constitute a channel region of the transistor. The IC device may also include one or more semiconductor structures that extend across an individual gate in the isolation region. An insulative structure may be formed between two gates in the isolation region. The insulative structure may be over the source or drain region.

Abstract: An IC device may include a support structure and a transistor built based on the support structure. The transistor may include an electrical contact over a semiconductor region in the transistor. The electrical contact may be a single structure formed by filling a single opening region with a conductive material. In an example, an end of the electrical contact may contact the semiconductor region, and another end of the electrical contact may contact a deep via. The deep via may extend through the support structure and contact a backside metal layer for delivering power or signal to the semiconductor region. In another example, an end of the electrical contact may contact the semiconductor region, and another end of the electrical contact may contact a semiconductor region in another transistor. A dielectric structure may be between the two semiconductor regions.

Abstract: Fabrication methods for integrated circuit (IC) structures and devices including asymmetric source and drain regions are described herein. In one example, an integrated circuit structure includes a transistor including a first region and a second region, where one of the first region and the second region is a source region of the transistor, and another of the first region and the second region is a drain region of the transistor, and where the first and second regions have different widths. In one example, the first region has a first width and the second region has a second width that is smaller than the first width.

Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include a conductive via with front-side and back-side connections with an S/D region are described herein. In one example, an IC structure includes a conductive via extending between a first layer and a second layer and an S/D region of a transistor between the first layer and the second layer, where the S/D region includes a first semiconductor material and a second semiconductor material. In one such example, the second semiconductor material may be epitaxially grown on the first semiconductor material of the S/D region from a back side of the IC structure. Conductive elements in layers over and under the conductive via may couple the conductive via with the S/D region from both the front-side and back-side S/D contact structures.

Abstract: Fabrication methods for integrated circuit (IC) structures and devices involving back-side nanoribbon removal are described herein. In one example, back-side nanoribbon removal involves providing stacks of nanoribbons from a first side of an IC structure, followed by removing one or more of the nanoribbons from a second side that is opposite the first side. In one example, an IC structure fabricated with back-side nanoribbon removal techniques may include a first stack of nanoribbons over a support and a second stack of nanoribbons over the support, where the number of nanoribbons in the first stack is less than in the second stack. A first transistor includes first channel regions in the nanoribbons of the first stack and a second transistor includes second channel regions in the nanoribbons of the second stack. Therefore, in one such example, the first transistor has channel regions in fewer nanoribbons than the second transistor.

Abstract: Fabrication methods for integrated circuit (IC) structures and devices with different nanoribbon thicknesses are disclosed. In one example, an IC structure includes a stack of nanoribbons stacked above one another over the support, including a first nanoribbon with a first channel region and a second nanoribbon with a second channel region, where the first channel region has a first thickness and the second channel region has a second thickness, and where the first thickness of the first channel region is different (e.g., greater) than the second thickness of the second channel region.

Abstract: IC devices with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as “angled” if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or a nanoribbon) based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to edges of front or back faces of a support structure on/in which the transistor resides, e.g., at an angle between 10 degrees and 80 degrees with respect to at least one of such edges. Angled transistors provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips.

Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.

Abstract: An IC device with one or more transistors may also include one or more vias and jumpers for delivering power to the transistors. For instance, a via may be coupled to a power plane. A jumper may be connected to the via and an electrode of a transistor. With the via and jumper, an electrical connection is built between the power plane and the electrode. The via may be self-aligned. The IC device may include a dielectric structure at a first side of the via. A portion of the jumper may be at a second side of the via. The second side opposes the first side. The dielectric structure and the portion of the jumper may be over another dielectric structure that has a different dielectric material from the dielectric structure. The via may be insulated from another electrode of the transistor, which may be coupled to a ground plane.

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

Abstract: An IC device may include memory layers over a logic layer. A memory layer may include memory arrays and one or more peripheral circuits coupled to the memory arrays. A memory array may include memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. The logic layer includes one or more logic circuits that can control data read operations and data write operations of the memory layers. The logic layer may also include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the IC device. The IC device may further include vias that couple the memory layers to the logic layer. Each via may be connected to one or more memory layers and the logic layer.

Abstract: An IC device may include memory layers bonded to a logic layer with inclination. An angle between a memory layer and the logic layer may be in a range from approximately 0 to approximately 90 degrees. The memory layers may be over the logic layer. The IC device may include one or more additional logic layers that are parallel to a memory layer or perpendicular to a memory layer. The one or more additional logic layers may be over the logic layer. A memory layer may include memory cells. The logic layer may include logic circuits (e.g., sense amplifier, word line driver, etc.) that control the memory cells. Bit lines (or word lines) in different memory layers may be coupled to each other. A bit line and a word line in a memory layer may be controlled by logic circuits in different logic layers.

Abstract: An IC device may include memory layers over a logic layer. A memory layer includes memory arrays, each of which includes memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. Bit lines of different memory arrays may be coupled using one or more vias or source/drain electrodes of transistors in the memory arrays. Alternatively, word lines of different memory arrays may be coupled using one or more vias or gate electrodes of transistors in the memory arrays. The logic layer has a logic circuit that can control data read operations and data write operations of the memory layers. The logic layer may include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the memory device.

Abstract: An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits, which may include MOSFET transistors. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. The logic circuits may include word line drivers and sense amplifiers. Word lines in different memory layers may share the same word line driver. Bit lines in different memory layers may share the same sense amplifier. The IC device may include front-back word line drivers, near-far sense amplifiers, near-far word line drivers, or front-back sense amplifiers. A memory layer may be bonded with the CMOS layer through a bonding layer that provides a bonding interface between the memory layer and the CMOS layer.