Patents by Inventor Anand S. Murthy

Anand S. Murthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250098179
    Abstract: An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits with MOSFET transistors. The CMOS layer may also include memory cells, e.g., SRAM cells. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. A logic circuit in the CMOS layer may control access to the memory cells. A memory layer may be bonded with the CMOS layer through a bonding layer that includes conductive structures coupled to a logic circuit in the CMOS layer or to bit lines or word lines in the memory layer. An additional conductive structure may be at the backside of a MOSFET transistor in the CMOS layer and coupled to a conductive structure in the bonding layer.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 20, 2025
    Inventors: Abhishek A. Sharma, Van H. Le, Fatih Hamzaoglu, Juan G. Alzate-Vinasco, Nikhil Jasvant Mehta, Vinaykumar Hadagali, Yu-Wen Huang, Honore Djieutedjeu, Tahir Ghani, Timothy Jen, Shailesh Kumar Madisetti, Jisoo Kim, Wilfred Gomes, Kamal Baloch, Vamsi Evani, Christopher Wiegand, James Pellegren, Sagar Suthram, Christopher M. Pelto, Gwang Soo Kim, Babita Dhayal, Prashant Majhi, Anand Iyer, Anand S. Murthy, Pushkar Sharad Ranade, Pooya Tadayon, Nitin A. Deshpande
  • Patent number: 12237420
    Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.
    Type: Grant
    Filed: April 23, 2024
    Date of Patent: February 25, 2025
    Assignee: Intel Corporation
    Inventors: Cory Bomberger, Anand S. Murthy, Tahir Ghani, Anupama Bowonder
  • Publication number: 20250022878
    Abstract: Methods for fabricating a transistor arrangement of an IC structure by using a placeholder for backside contact formation, as well as related semiconductor devices, are disclosed. An example method includes forming, in a support structure (e.g., a substrate, a chip, or a wafer), a dielectric placeholder for a backside contact as the first step in the method. A nanosheet superlattice is then grown laterally over the dielectric placeholder, and a stack of nanoribbons is formed based on the superlattice. The nanoribbons are processed to form S/D regions and gate stacks for future transistors. The dielectric placeholder remains in place until the support structure is transferred to a carrier wafer, at which point the dielectric placeholder is replaced with the backside contact. Use of a placeholder for backside contact formation allows alignment of contact from the backside to appropriate device ports of a transistor arrangement.
    Type: Application
    Filed: October 1, 2024
    Publication date: January 16, 2025
    Applicant: Intel Corporation
    Inventors: Andy Chih-Hung Wei, Anand S. Murthy, Mauro J. Kobrinsky, Guillaume Bouche
  • Publication number: 20250008723
    Abstract: Integrated circuit (IC) devices implementing three-dimensional (3D) floating body memory are disclosed. An example IC device includes a floating body memory cell comprising a transistor having a first source or drain (S/D) region, a second S/D region, and a gate over a channel portion between the first and second S/D regions; a BL coupled to the first S/D region and parallel to a first axis of a Cartesian coordinate system; a SL coupled to the second S/D region and parallel to a second axis of the coordinate system; and a WL coupled to or being a part of the gate and parallel to a third axis of the coordinate system. IC devices implementing 3D floating body memory as described herein may be used to address the scaling challenges of conventional memory technologies and enable high-density embedded memory compatible with advanced CMOS processes.
    Type: Application
    Filed: June 27, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Wilfred Gomes, Tahir Ghani, Anand S. Murthy, Sagar Suthram
  • Publication number: 20240429162
    Abstract: An example IC device includes a substrate comprising a plurality of areas and one or more scribe lines defining boundaries of individual areas of the plurality of areas. The plurality of areas includes a first area and a second area. The IC device further includes a scribe line between the first area and the second area, a first device layer over the first area of the substrate and a first metallization stack over the first device layer, a second device layer over the second area of the substrate and a second metallization stack over the second device layer, and a conductive line extending (e.g., being materially and electrically continuous) between the first metallization stack and the second metallization stack, where a projection of the conductive line onto a plane parallel to the substrate and containing the scribe line intersects the scribe line.
    Type: Application
    Filed: June 23, 2023
    Publication date: December 26, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Tahir Ghani, Sagar Suthram, Anand S. Murthy, Wilfred Gomes
  • Publication number: 20240431092
    Abstract: A transistor may include a source region, a drain region, a channel region between the source region and the drain region in a first direction, a gate electrode, a source contact, and a drain contact. A first portion of the gate electrode is over the channel region in a second direction substantially perpendicular to the first direction. A second portion of the gate electrode is over a first portion of the drain region in the second direction. The source contact is over at least part of the source region. The drain contact is over a second portion of the drain region. A distance from an edge of the first portion of the drain region to an edge of the gate electrode or to an edge the first trench electrode in the first direction is greater than a fourth of a length of the gate electrode in the first direction.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 26, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Wilfred Gomes, Tahir Ghani, Anand S. Murthy
  • Publication number: 20240431117
    Abstract: IC devices implementing memory with one access transistor coupled to multiple capacitors are disclosed. An example IC device includes a support structure (e.g., a substrate), an access transistor over the support structure, the access transistor having a region that is either a source region or a drain region, and a plurality of capacitors where at least two or more of the capacitors are in different layers above the access transistor. First capacitor electrodes of the plurality of capacitors are coupled to the region, and second capacitor electrodes of the plurality of capacitors are coupled to respective electrically conductive lines. IC devices implementing memory with one access transistor coupled to multiple capacitors as described herein may be used to address the scaling challenges of conventional 1T-1C memory technology and enable high-density embedded memory compatible with advanced CMOS processes.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 26, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Wilfred Gomes, Tahir Ghani, Anand S. Murthy
  • Patent number: 12170319
    Abstract: Embodiments disclosed herein include complementary metal-oxide-semiconductor (CMOS) devices and methods of forming CMOS devices. In an embodiment, a CMOS device comprises a first transistor with a first conductivity type, where the first transistor comprises a first source region and a first drain region, and a first metal over the first source region and the first drain region. In an embodiment, the CMOS device further comprises a second transistor with a second conductivity type opposite form the first conductivity type, where the second transistor comprises a second source region and a second drain region, a second metal over the second source region and the second drain region, and the first metal over the second metal.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: December 17, 2024
    Assignee: Intel Corporation
    Inventors: Kevin Cook, Anand S. Murthy, Gilbert Dewey, Nazila Haratipour, Ralph Thomas Troeger, Christopher J. Jezewski, I-Cheng Tung
  • Patent number: 12166124
    Abstract: Gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. Individual ones of the vertical arrangement of nanowires have a relatively higher germanium concentration at a lateral mid-point of the nanowire than at lateral ends of the nanowire.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: December 10, 2024
    Assignee: Intel Corporation
    Inventors: Ryan Hickey, Glenn A. Glass, Anand S. Murthy, Rushabh Shah, Ju-Hyung Nam
  • Patent number: 12148751
    Abstract: Methods for fabricating a transistor arrangement of an IC structure by using a placeholder for backside contact formation, as well as related semiconductor devices, are disclosed. An example method includes forming, in a support structure (e.g., a substrate, a chip, or a wafer), a dielectric placeholder for a backside contact as the first step in the method. A nanosheet superlattice is then grown laterally over the dielectric placeholder, and a stack of nanoribbons is formed based on the superlattice. The nanoribbons are processed to form S/D regions and gate stacks for future transistors. The dielectric placeholder remains in place until the support structure is transferred to a carrier wafer, at which point the dielectric placeholder is replaced with the backside contact. Use of a placeholder for backside contact formation allows alignment of contact from the backside to appropriate device ports of a transistor arrangement.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: November 19, 2024
    Assignee: Intel Corporation
    Inventors: Andy Chih-Hung Wei, Anand S. Murthy, Mauro J. Kobrinsky, Guillaume Bouche
  • Patent number: 12119387
    Abstract: Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Nazila Haratipour, Siddharth Chouksey, Jack T. Kavalieros, Jitendra Kumar Jha, Matthew V. Metz, Mengcheng Lu, Anand S. Murthy, Koustav Ganguly, Ryan Keech, Glenn A. Glass, Arnab Sen Gupta
  • Patent number: 12107085
    Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure.
    Type: Grant
    Filed: July 7, 2023
    Date of Patent: October 1, 2024
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang, Christopher Jezewski, Ehren Mannebach, Rishabh Mehandru, Patrick Morrow, Anand S. Murthy, Anh Phan, Willy Rachmady
  • Publication number: 20240321859
    Abstract: An IC device may include an array of transistors. The transistors may have separate gate electrodes. A gate electrode may include polysilicon. The gate electrodes may be separated from each other by one or more electrical insulators. The separated gate electrodes have shorter lengths, compared with connected gate electrodes, which can optimize the performance of the IC device due to local layout effect. Also, the IC device may include conductive structures crossing the support structures of multiple transistors. Such conductive structures may cause strain in the IC device, which can boost the local layout effect. The conductive structures may be insulated from a power plane. Alternatively or additionally, the IC device may include dielectric structures, which may be formed by removing gate electrodes in some of the transistors and providing a dielectric material into the openings. The presence of the dielectric structures can further boost the local layout effect.
    Type: Application
    Filed: March 22, 2023
    Publication date: September 26, 2024
    Applicant: Intel Corporation
    Inventors: Tao Chu, Minwoo Jang, Yanbin Luo, Paul Packan, Guowei Xu, Chiao-Ti Huang, Robin Chao, Feng Zhang, Anand S. Murthy, Tahir Ghani
  • Publication number: 20240321987
    Abstract: Described herein are integrated circuit devices that include both nanoribbon-based transistors and fin-shaped transistors. The nanoribbon transistors may have shorter channel lengths than the fin transistors. In addition, the nanoribbon transistors may have thinner gate dielectrics than the fin transistors.
    Type: Application
    Filed: March 22, 2023
    Publication date: September 26, 2024
    Applicant: Intel Corporation
    Inventors: Tao Chu, Guowei Xu, Robin Chao, Chiao-Ti Huang, Feng Zhang, Minwoo Jang, Chia-Ching Lin, Biswajeet Guha, Yue Zhong, Anand S. Murthy
  • Publication number: 20240290788
    Abstract: A metal gate fabrication method for nanoribbon-based transistors and associated transistor arrangements, IC structures, and devices are disclosed. An example IC structure fabricated using metal gate fabrication method described herein may include a first stack of N-type nanoribbons, a second stack of P-type nanoribbons, a first gate region enclosing portions of the nanoribbons of the first stack and including an NWF material between adjacent nanoribbons of the first stack, and a second gate region enclosing portions of the nanoribbons of the second stack and including a PWF material between adjacent nanoribbons of the second stack, where the second gate region includes the PWF material at sidewalls of the nanoribbons of the second stack and further includes the NWF material so that the PWF material is between the sidewalls of the nanoribbons of the second stack and the NWF material.
    Type: Application
    Filed: February 28, 2023
    Publication date: August 29, 2024
    Applicant: Intel Corporation
    Inventors: Guowei Xu, Tao Chu, Chiao-Ti Huang, Robin Chao, David Towner, Orb Acton, Omair Saadat, Feng Zhang, Dax M. Crum, Yang Zhang, Biswajeet Guha, Oleg Golonzka, Anand S. Murthy
  • Patent number: 12046600
    Abstract: Techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. In some cases, multiple fin dimensions are achieved by lithographically defining (e.g., hardmasking and patterning) areas to be trimmed using a trim etch process, leaving the remainder of the die unaffected. In some such cases, the trim etch is performed on only the channel regions of the fins, when such channel regions are re-exposed during a replacement gate process. The trim etch may narrow the width of the fins being trimmed (or just the channel region of such fins) by 2-6 nm, for example. Alternatively, or in addition, the trim may reduce the height of the fins. The techniques can include any number of patterning and trimming processes to enable a variety of fin dimensions and/or fin channel dimensions on a given die, which may be useful for integrated circuit and system-on-chip (SOC) applications.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: July 23, 2024
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy
  • Patent number: 12046517
    Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: July 23, 2024
    Assignee: Tahoe Research, Ltd.
    Inventors: Glenn A. Glass, Daniel B. Aubertine, Anand S. Murthy, Gaurav Thareja, Tahir Ghani
  • Patent number: 12046654
    Abstract: Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi2.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: July 23, 2024
    Assignee: Intel Corporation
    Inventors: Dan S. Lavric, Glenn A. Glass, Thomas T. Troeger, Suresh Vishwanath, Jitendra Kumar Jha, John F. Richards, Anand S. Murthy, Srijit Mukherjee
  • Patent number: 12027417
    Abstract: Integrated circuit structures having source or drain structures with a high germanium concentration capping layer are described. In an example, an integrated circuit structure includes source or drain structures including an epitaxial structure embedded in a fin at a side of a gate stack. The epitaxial structure has a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer with an abrupt interface between the capping semiconductor layer and the lower semiconductor layer. The lower semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of less than 40% at the abrupt interface. The capping semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of greater than 50% at the abrupt interface and throughout the capping semiconductor layer.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: July 2, 2024
    Assignee: Intel Corporation
    Inventors: Cory Bomberger, Suresh Vishwanath, Yulia Tolstova, Pratik Patel, Szuya S. Liao, Anand S. Murthy
  • Patent number: 12021149
    Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: June 25, 2024
    Assignee: Intel Corporation
    Inventors: Cory Bomberger, Anand S. Murthy, Tahir Ghani, Anupama Bowonder