Abstract: A method to form a strain-inducing epitaxial film is described. In one embodiment, the strain-inducing epitaxial film is a three-component epitaxial film comprising atoms from a parent film, charge-neutral lattice-substitution atoms and charge-carrier dopant impurity atoms. In another embodiment, the strain-inducing epitaxial film is formed by a multiple deposition/etch cycle sequence involving hydrogenated amorphous silicon, followed by charge carrier dopant and charge-neutral lattice-forming impurity atom implant steps and, finally, a kinetically-driven crystallization process.

Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics.

Abstract: A method and information processing system for wirelessly transmitting at least one of a downlink channel descriptor and an uplink channel descriptor for reception by at least one wireless device (104). The method comprises selecting at least one transmission time for transmitting a pointer that indicates a transmission time for a DCD and/or a UCD. The pointer is transmitted at a time between a first transmission and a second transmission of the at least one of downlink channel descriptor and uplink channel descriptor. The transmission time is selected to reduce a time interval for the at least one wireless device (104) to search for the at least one of the DCD and UCD. Also, a message that includes DCD information and/or UCD information associated with at least one neighboring cell can also be chosen to transmit at specifically chosen times to the at least one wireless device (104).

Abstract: A VLAN tagging unit associated with a WAN is used to add VLAN tags based upon logical interfaces. In one example, data received across the logical interface is tagged with an associated VLAN ID by the unit. In another embodiment, flow-based VLAN tagging is done in which in addition to the logical interface other indications are used in the VLAN tagging.

Abstract: An epitaxially deposited source/drain extension may be formed for a metal oxide semiconductor field effect transistor. A sacrificial layer may be formed and etched away to undercut under the gate electrode. Then a source/drain extension of epitaxial silicon may be deposited to extend under the edges of the gate electrode. As a result, the extent by which the source/drain extension extends under the gate may be controlled by controlling the etching of the sacrificial material. Its thickness and depth may be controlled by controlling the deposition process. Moreover, the characteristics of the source/drain extension may be controlled independently of those of the subsequently formed deep or heavily doped source/drain junction.

Abstract: A communication system that includes multiple nodes controls a flow of data from a first node of the multiple nodes to a second node of the multiple nodes without relying on an estimate of a rate at which data is drawn from a buffer of the second node and such that an overflow and an underflow of the buffer is avoided. The second node determines multiple flow control parameters, including a current occupancy (Q) of the buffer and an upper threshold (U) and a lower threshold (L) for an occupancy of the buffer and determines a desired data rate (r) based on the multiple flow control parameters. The desired data rate can be used to adjust a data rate for the flow of data. In another embodiment, the communication system further dynamically controls a rate at which flow control messages are conveyed by the second node to the first node.

Abstract: A method is described for forming an element of a microelectronic circuit. A sacrificial layer is formed on an upper surface of a support layer. The sacrificial layer is extremely thin and uniform. A height-defining layer is then formed on the sacrificial layer, whereafter the sacrificial layer is etched away so that a well-defined gap is left between an upper surface of the support layer and a lower surface of the height-defining layer. A monocrystalline semiconductor material is then selectively grown from a nucleation silicon site through the gap. The monocrystalline semiconductor material forms a monocrystalline layer having a thickness corresponding to the thickness of the original sacrificial layer.

Abstract: Transistors are manufactured by growing germanium source and drain regions, implanting dopant impurities into the germanium, and subsequently annealing the source and drain regions so that the dopant impurities diffuse through the germanium. The process is simpler than a process wherein germanium is insitu doped with p-type or n-type impurities. The dopant impurities diffuse easily through the germanium but not easily through underlying silicon, so that an interface between the germanium and silicon acts as a diffusion barrier and ensures positioning of the dopant atoms in the regions of the device where they improve transistor performance.

Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer (108) adjacent to the vertical sidewalls of the gate electrode (106), or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics.

Abstract: Transistors are manufactured by growing germanium source and drain regions, implanting dopant impurities into the germanium, and subsequently annealing the source and drain regions so that the dopant impurities diffuse through the germanium. The process is simpler than a process wherein germanium is insitu doped with p-type or n-type impurities. The dopant impurities diffuse easily through the germanium but not easily through underlying silicon, so that an interface between the germanium and silicon acts as a diffusion barrier and ensures positioning of the dopant atoms in the regions of the device where they improve transistor performance.

Abstract: A method is described for forming an element of a microelectronic circuit. A sacrificial layer is formed on an upper surface of a support layer. The sacrificial layer is extremely thin and uniform. A height-defining layer is then formed on the sacrificial layer, whereafter the sacrificial layer is etched away so that a well-defined gap is left between an upper surface of the support layer and a lower surface of the height-defining layer. A monocrystalline semiconductor material is then selectively grown from a nucleation silicon site through the gap. The monocrystalline semiconductor material forms a monocrystalline layer having a thickness corresponding to the thickness of the original sacrificial layer.

Abstract: A communication system that includes multiple nodes controls a flow of data from a first node of the multiple nodes to a second node of the multiple nodes without relying on an estimate of a rate at which data is drawn from a buffer of the second node and such that an overflow and an underflow of the buffer is avoided. The second node determines multiple flow control parameters, including a current occupancy (Q) of the buffer and an upper threshold (U) and a lower threshold (L) for an occupancy of the buffer and determines a desired data rate (r) based on the multiple flow control parameters. The desired data rate can be used to adjust a data rate for the flow of data. In another embodiment, the communication system further dynamically controls a rate at which flow control messages are conveyed by the second node to the first node.

Abstract: A base station of a code division, multiple access (CDMA) telecommunications system employs scheduling of data transmission signals to corresponding user transceivers in down-link channels of a data network. One or more user transceivers may be in communication with a base station within a cell, and each user may have a minimum data rate requirement. In accordance with the present invention, the scheduling of user data transmission follows the constraints that 1) each base station transmits to user transceivers one at a time, and 2) the base station uses full available power for the down-link channel when transmitting (for data networks only). Given a data network of users, the method of scheduling and data rates may be modeled in accordance with a linear programming problem optimized according to a predefined criterion. In addition, the present method may be employed in a hybrid CDMA/time-share system to reduce power of data channels in communication with user transceivers near the base station.

Abstract: Transistors are manufactured by growing germanium source and drain regions, implanting dopant impurities into the germanium, and subsequently annealing the source and drain regions so that the dopant impurities diffuse through the germanium. The process is simpler than a process wherein germanium is insitu doped with p-type or n-type impurities. The dopant impurities diffuse easily through the germanium but not easily through underlying silicon, so that an interface between the germanium and silicon acts as a diffusion barrier and ensures positioning of the dopant atoms in the regions of the device where they improve transistor performance.

Abstract: A stressed channel is formed in a PMOS transistor by etching a recess and subsequently backfilling the recess with an epitaxially formed alloy of silicon, germanium, and an n-type dopant. The alloy has the same crystal structure as the underlying silicon, but the spacing of the crystal is larger, due to the inclusion of the germanium. An NMOS transistor can be formed by including carbon instead of germanium.

Abstract: A base station of a code division, multiple access (CDMA) telecommunications system employs scheduling of data transmission signals to corresponding user transceivers in down-link channels of a data network. One or more user transceivers may be in communication with a base station within a cell, and each user may have a minimum data rate requirement. In accordance with the present invention, the scheduling of user data transmission follows the constraints that 1) each base station transmits to user transceivers one at a time, and 2) the base station uses full available power for the down-link channel when transmitting (for data networks only). Given a data network of users, the method of scheduling and data rates may be modeled in accordance with a linear programming problem optimized according to a predefined criterion. In addition, the present method may be employed in a hybrid CDMA/time-share system to reduce power of data channels in communication with user transceivers near the base station.

Abstract: A microelectronic structure includes at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type. In a further aspect of the invention, a process for forming a microelectronic structure, such as a MOSFET, having at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type includes forming a recess having a surface, forming a dielectric material over a portion of the surface of the recess, and back-filling the recess to from a source/drain terminal.

Abstract: A microelectronic structure includes at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type. In a further aspect of the invention, a process for forming a microelectronic structure, such as a MOSFET, having at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type includes forming a recess having a surface, forming a dielectric material over a portion of the surface of the recess, and back-filling the recess to form a source/drain terminal.

Abstract: A process for removing dissolved uranium from water is provided. The process basically comprises (a) mixing phosphoric acid or particulate bone ash with the water, (b) mixing calcium hydroxide with the mixture produced in step (a) to thereby form calcium hydroxy phosphate or calcium hydroxy apatite which reacts with and complexes at least a portion of the uranium in the water to form a precipitate thereof, and (c) separating the precipitate from the water.

Abstract: A VLAN tagging unit associated with a WAN is used to add VLAN tags based upon logical interfaces. In one example, data received across the logical interface is tagged with an associated VLAN ID by the unit. In another embodiment, flow-based VLAN tagging is done in which in addition to the logical interface other indications are used in the VLAN tagging.