Patents by Inventor Anand S

Anand S has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110025566
    Abstract: A near-horizon antenna structure includes an upper radiating element having a straight conductive trace disposed on a planar surface of a non-conductive substrate, a rectangular lower radiating element serving as a ground plane disposed on the planar surface, and a feed point provided between the upper and lower radiating elements. When the planar surface is positioned vertically, the far-field effects of horizontal current flowing in opposite directions on the radiating elements cancel to provide an antenna pattern with increased gain in horizontal directions and reduced gain in vertical directions. A flat panel display and a portable communication device are also provided with one or more near-horizon antenna structures integrated therein.
    Type: Application
    Filed: July 31, 2009
    Publication date: February 3, 2011
    Inventors: Seong-Youp Suh, Anand S. Konanur, Songnan Yang, Salih Yarga
  • Patent number: 7833883
    Abstract: A precursor gas mixture for depositing an epitaxial carbon-doped silicon film is described. The precursor gas mixture is comprised of a volume of a silicon precursor gas, a volume of acetylene gas and a volume of a carrier gas. A method of forming a semiconductor structure having an epitaxial carbon-doped silicon film is also described. In the method, a substrate having a high polarity dielectric region and a low polarity crystalline region is provided. A precursor gas is flowed to provide a silyl surface above the high polarity dielectric region and a carbon-doped silicon layer above the low polarity crystalline region. The silyl surface is then removed from above the high polarity dielectric region. The flowing and removing steps are repeated to provide a carbon-doped silicon film of a desired thickness above the low polarity crystalline region.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: November 16, 2010
    Assignee: Intel Corporation
    Inventors: Danielle M. Simonelli, Anand S. Murthy, Daniel B. Aubertine
  • Publication number: 20100271962
    Abstract: A method and apparatus for estimating an available backhaul bandwidth in a femto-cell communication network includes a step (204, 304) of sending at least one defined data stream to at least one femto-cell. A next step (206, 306) includes measuring a delay of the at least one defined data stream at the at least one femto-cell. A next step (208, 308) includes estimating, from the delay of the at least one defined data stream, a backhaul bandwidth availability.
    Type: Application
    Filed: April 22, 2009
    Publication date: October 28, 2010
    Applicant: MOTOROLA, INC.
    Inventors: Guang Han, Rajeev Agrawal, Anand S. Bedekar
  • Patent number: 7821044
    Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: October 26, 2010
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Steven J. Keating, Thomas A. Letson, Anand S. Murthy, Donald W. O'Neill, Willy Rachmady
  • Publication number: 20100235615
    Abstract: A method for discovery of a root file system that includes obtaining a tag corresponding to a boot image for an operating system, identifying, by a boot loader, a location of the boot image having a predefined value matching the tag, loading a kernel of the operating system retrieved from the boot image, and transferring execution to the kernel, wherein the boot loader provides the tag for the location to the kernel. The method further includes identifying, by the kernel, the location of the root file system based on the tag provided by the boot loader, and executing the operating system on a processor using the root file system identified by the kernel.
    Type: Application
    Filed: March 13, 2009
    Publication date: September 16, 2010
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Olaf Manczak, Anand S. Gupta, Christopher A. Vick
  • Patent number: 7751165
    Abstract: A centrally controlled protection system is provided. The system includes a plurality of circuit breakers, a plurality of modules, and a central computer. Each of the plurality of breakers are in electrical communication with a respective one of the plurality of modules. The central computer is in communication with each of the plurality of modules via a network. The central computer controls the plurality of circuit breakers in either a normal mode or a reduced energy let-through mode.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: July 6, 2010
    Assignee: General Electric Company
    Inventors: Anand S. V. Sirivella, Thomas Papallo, Gregory P. Lavoie, Theodore D. Hill, III, Radoslaw Narel, Marcelo Valdes
  • Publication number: 20100151669
    Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
    Type: Application
    Filed: February 26, 2010
    Publication date: June 17, 2010
    Inventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
  • Publication number: 20100133595
    Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics.
    Type: Application
    Filed: February 4, 2010
    Publication date: June 3, 2010
    Inventors: Anand S. Murthy, Robert S. Chau, Patrick Morrow, Chia-Hong Jan, Paul Packan
  • Patent number: 7704833
    Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
  • Publication number: 20100081388
    Abstract: A first base station communicates (102) with a second base station (wherein an ongoing communication cannot be handed over from the first base station to the second base station and wherein the first and second base station each employ, at least in part, a same set of carrier resources) to prevent interference by usage of the second base station with a user of the first base station. By one approach, this activity can be based, at least in part, upon receipt (101) of a message from an end user platform indicating that a carrier resource that is presently being used by the end user platform is being interfered with by the second base station. By another approach, this activity can take place prior to any actual such interference.
    Type: Application
    Filed: August 13, 2009
    Publication date: April 1, 2010
    Applicant: MOTOROLA, INC.
    Inventors: Guang Han, Rajeev Agrawal, Anand S. Bedekar
  • Patent number: 7682916
    Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: March 23, 2010
    Assignee: Intel Corporation
    Inventors: Anand S. Murthy, Robert S. Chau, Patrick Morrow, Chia-Hong Jan, Paul Packan
  • Publication number: 20100068132
    Abstract: A shared or common environment membrane reactor containing a plurality of planar membrane modules with top and bottom thin foil membranes supported by both an intermediary porous support plate and a central base which has both solid extended members and hollow regions or a hollow region whereby the two sides of the base are in fluid communication. The membrane reactor operates at elevate temperatures for generating hydrogen from hydrogen rich feed fuels.
    Type: Application
    Filed: March 19, 2009
    Publication date: March 18, 2010
    Inventors: Thomas R. Vencill, Anand S. Chellappa, Shailendra B. Rathod
  • Patent number: 7680063
    Abstract: A method and apparatus for transmitting packets in a wireless communication system (100). The method and apparatus determining a delay period from among the various delay times at each of a plurality of access nodes (106-110) wherein the delay time is the time it takes for a node to receive a data packet from a source (102) through a network (104). During transmission of data from the source, the nodes receive data packets and from the data packets, the wall clock time is determined. The packets are transmitted from the nodes at a time equivalent to the wall clock time and the delay period so that the packets are synchronously transmitted from the multiple nodes.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: March 16, 2010
    Assignee: Motorola, Inc.
    Inventors: Anand S. Bedekar, Rajeev Agrawal
  • Publication number: 20100054237
    Abstract: Timing synchronization between base stations of uncoordinated communication networks includes obtaining timing synchronization information from one base station, and adjusting a clock of the other station in response to the synchronization information. The timing synchronization information can be identified from a strongest synchronization signal from nearby uncoordinated base stations. The timing synchronization can accommodate clock offsets and frequency offsets.
    Type: Application
    Filed: July 27, 2009
    Publication date: March 4, 2010
    Applicant: MOTOROLA, INC.
    Inventors: Guang Han, Rajeev Agrawal, Anand S. Bedekar
  • Publication number: 20090305423
    Abstract: Methods for evaluating cheese comprising using a rapid extraction method and an IR spectra analysis of the cheese are disclosed.
    Type: Application
    Filed: June 9, 2009
    Publication date: December 10, 2009
    Applicant: Ohio State University Research Foundation
    Inventors: Anand S. Subramanian, Luis E. Rodriguez-Saona
  • Publication number: 20090248841
    Abstract: A method (500) and a system (300) for implementing point-to-point communications. The method can include identifying at least a first portion (348, 350) of a prefix (344, 346) of a network address, the prefix corresponding to a particular topological region (326, 328) of a communications network (302). The method further can include generating a unique prefix (360, 362) by updating the prefix with an identifier (356, 358) that is unique within the topological region of the communications network, and assigning the unique prefix to a node (304-314) of the communications network.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Applicant: MOTOROLA, INC.
    Inventors: Paula Tjandra, Anand S. Bedekar, Philip R. Roberts, Ajoy K. Singh
  • Publication number: 20090093709
    Abstract: In one aspect, a method for noise reduction in parallel magnetic resonance (MR) imaging using a plurality of radio frequency (RF) coils is provided. The method comprises performing a first MR scan of a target to obtain first MR data, performing a second MR scan of the target to obtain second MR data, the second MR data obtained from operating the plurality of coils substantially in parallel, computing a noise estimate associated with the second MR data based at least in part on the first and second MR data, and obtaining a noise-reduced image based at least in part on the second MR data and the noise estimate.
    Type: Application
    Filed: May 19, 2008
    Publication date: April 9, 2009
    Applicant: Beth Israel Deaconess Medical Center, Inc.
    Inventors: Anand S. Patel, Philip M. Robson, Charles A. McKenzie, Daniel K. Sodickson
  • Publication number: 20090058751
    Abstract: A balanced antenna is integrated into a wireless mobile device, such as a laptop computer, for improved antenna reception. The antenna is connected to a radio frequency (RF) interconnection cable. A balun is disposed between the antenna and the cable. By using a balanced antenna, the fraction of the noise produced by the motherboard and display of the wireless mobile device that is captured by the antenna is significantly reduced compared to that captured by an unbalanced antenna, and thus not captured by the antenna.
    Type: Application
    Filed: August 28, 2007
    Publication date: March 5, 2009
    Inventors: SEONG-YOUP SUH, KWAN-HO LEE, ANAND S. KONANUR
  • Patent number: 7494858
    Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: February 24, 2009
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Steven J. Keating, Thomas A. Letson, Anand S. Murthy, Donald W. O'Neill, Willy Rachmady
  • Publication number: 20090011565
    Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics.
    Type: Application
    Filed: August 28, 2008
    Publication date: January 8, 2009
    Inventors: Anand S. Murthy, Robert S. Chau, Patrick Morrow, Chia-Hong Jan, Paul Packan