Abstract: A system is disclosed. The system may include a computer system, which may include a processor that may execute instructions of an application that accesses an object using an object command, and a memory storing the instructions of the application. The computer system may also include a conversion module to convert the object command to a key-value (KV) command. Finally, the system may include a storage device storing data for the object and processing the object using the KV command.

Abstract: The present disclosure relates to adapter assemblies for use with and to electrically and mechanically interconnect electromechanical surgical devices and surgical loading units, and to surgical systems including hand held electromechanical surgical devices and adapter assemblies for connecting surgical loading units to the hand held electromechanical surgical devices.

Abstract: Techniques are disclosed performing a power logging in a computer system at a sub-process level. An exemplary method includes an operating system of the computer system determining process information indicative of which sub-portions of one or more processes are running on the computer system at different points in time, as well as may determining power information for the computer system at different points in time. The operating system may the create, from the process information and the power information, a power log indicative of power usage of sub-portions of processes at a plurality of points in time. The power logging may extend to both core and non-core resources of the system. For non-core resources, the power usage may be estimated in some cases based on the type of non-core resource being called as well as parameters passed to the non-core resource.

Abstract: A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE) having an AFE input and an AFE output. The AFE output is coupled the ADC's input. The AFE includes a programmable gain amplifier (PGA) having a first PGA input and a second PGA input. The PGA includes a first operational amplifier (OP AMP) with first and second OPAMP inputs. The AFE also including a programmable resistance circuit having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit includes a resistor network having first and second balance resistances. The first balance resistance is coupled to the first and second OP AMP inputs, and the second balance resistance is coupled to the first and second OP AMP inputs.

Abstract: An adapter assembly includes an elongated body, a switch, a sensor link, and an annular member. The elongated body includes a proximal portion configured to couple to a handle assembly and a distal portion configured to couple to a surgical loading unit. The switch is configured to be toggled in response to the surgical loading unit being coupled to the distal portion of the adapter assembly. The sensor link is disposed within the distal portion of the adapter assembly and biased toward a distal position. The sensor link is longitudinally movable between a proximal position and the distal position. The annular member is disposed within the distal portion and is rotatable between a first orientation, in which the annular member prevents distal movement of the sensor link, and a second orientation, in which the sensor link moves distally to toggle the switch.

Abstract: An adapter assembly includes an elongated body, a switch, a sensor link, and an annular member. The elongated body includes a proximal portion configured to couple to a handle assembly and a distal portion configured to couple to a surgical loading unit. The switch is configured to be toggled in response to the surgical loading unit being coupled to the distal portion of the adapter assembly. The sensor link is disposed within the distal portion of the adapter assembly and biased toward a distal position. The sensor link is longitudinally movable between a proximal position and the distal position. The annular member is disposed within the distal portion and is rotatable between a first orientation, in which the annular member prevents distal movement of the sensor link, and a second orientation, in which the sensor link moves distally to toggle the switch.

Abstract: The present disclosure relates to adapter assemblies for use with and to electrically and mechanically interconnect electromechanical surgical devices and surgical loading units, and to surgical systems including hand held electromechanical surgical devices and adapter assemblies for connecting surgical loading units to the hand held electromechanical surgical devices.

Abstract: Annotating time series data points with alert information is described. A system retrieves a time series data point and a corresponding alert trigger condition from a time series database. The system evaluates whether the time series data point meets the corresponding alert trigger condition. The system outputs an alert notification associated with the time series data point and the corresponding alert trigger condition if the time series data point meets the corresponding alert trigger condition. The system annotates the time series data point, in the time series database, with alert information associated with the corresponding alert trigger condition if the time series data point meets the corresponding alert trigger condition.

Abstract: A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE) having an AFE input and an AFE output. The AFE output is coupled the ADC's input. The AFE includes a programmable gain amplifier (PGA) having a first PGA input and a second PGA input. The PGA includes a first operational amplifier (OP AMP) with first and second OPAMP inputs. The AFE also including a programmable resistance circuit having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit includes a resistor network having first and second balance resistances. The first balance resistance is coupled to the first and second OP AMP inputs, and the second balance resistance is coupled to the first and second OP AMP inputs.

Abstract: A chopper-stabilized amplifier includes a first transconductance amplifier and a first chopper circuit coupled to an input of the first transconductance amplifier. A second chopper circuit is coupled to an output of the first transconductance amplifier. The chopper-stabilized amplifier also includes second and third transconductance amplifiers having inputs coupled to the output of the first transconductance amplifier. The second transconductance amplifier produces an output responsive to a first notch clock signal having a first phase relative to the chopping of the second chopper circuit. The third transconductance amplifier produces an output responsive to a second notch clock signal having a second phase relative to the first phase. The output signals produced by the second and third transconductance amplifiers are added to filter ripple noise at the outputs of the second and third transconductance amplifiers.

Abstract: A circuit includes first and second gain stages and an output transistor. The second gain stage includes a transconductance amplifier and a variable impedance circuit coupled to an output of the transconductance amplifier. The variable impedance circuit is configured to implement a first impedance level at frequencies below a first frequency threshold and to implement a second impedance level at frequencies above a second frequency level. The first impedance level is larger than the second impedance level. The output transistor has a control input coupled to the variable impedance circuit. At frequencies above the second frequency threshold, the second impedance level is configured to be inversely related to current through the output transistor.

Abstract: A desolidification process enables the isolation and extraction of solid additives from an unreacted petroleum residue stream. In a hydrocracking process that mixes a solid additive with a petroleum residue feedstock to convert the petroleum residue to higher-value distillates, the desolidification process enables the recovery of the unreacted petroleum residue for conversion to a saleable product. The desolidification process involves the mixture of one or more solvents with a slurry in which solids are integrated in the petroleum residue to generate a mixture having a decreased density and viscosity as compared to the slurry, which facilitates removal of the solids.

Abstract: The present disclosure relates to adapter assemblies for use with and to electrically and mechanically interconnect electromechanical surgical devices and surgical loading units, and to surgical systems including hand held electromechanical surgical devices and adapter assemblies for connecting surgical loading units to the hand held electromechanical surgical devices.

Abstract: A circuit includes first and second gain stages and an output transistor. The second gain stage includes a transconductance amplifier and a variable impedance circuit coupled to an output of the transconductance amplifier. The variable impedance circuit is configured to implement a first impedance level at frequencies below a first frequency threshold and to implement a second impedance level at frequencies above a second frequency level. The first impedance level is larger than the second impedance level. The output transistor has a control input coupled to the variable impedance circuit. At frequencies above the second frequency threshold, the second impedance level is configured to be inversely related to current through the output transistor.

Abstract: A circuit includes first and second gain stages and an output transistor. The second gain stage includes a transconductance amplifier and a variable impedance circuit coupled to an output of the transconductance amplifier. The variable impedance circuit is configured to implement a first impedance level at frequencies below a first frequency threshold and to implement a second impedance level at frequencies above a second frequency level. The first impedance level is larger than the second impedance level. The output transistor has a control input coupled to the variable impedance circuit. At frequencies above the second frequency threshold, the second impedance level is configured to be inversely related to current through the output transistor.

Abstract: A circuit includes a programmable gain amplifier (PGA) having a PGA output. The circuit further includes a delta-sigma modulator having an input coupled to the PGA output. The circuit also includes a digital filter and a dynamic range enhancer (DRE) circuit. The digital filter is coupled to the delta-sigma modulator output. The DRE circuit is coupled to the delta-sigma modulator output and to the PGA. The DRE circuit is configured to monitor a signal level of the delta-sigma modulator output. Responsive to the signal level being less than a DRE threshold, the DRE circuit is configured to program the PGA for a gain level greater than unity gain and to cause the digital filter to implement an attenuation of a same magnitude as the gain level to be programmed into the PGA.

Abstract: The present disclosure relates to adapter assemblies for use with and to electrically and mechanically interconnect electromechanical surgical devices and surgical loading units, and to surgical systems including hand held electromechanical surgical devices and adapter assemblies for connecting surgical loading units to the hand held electromechanical surgical devices.

Abstract: A storage node in a cluster of storage nodes includes: one or more local storage devices; and a storage node controller. The storage node controller includes: a host interface configured to connect to an application running on a host computer; a storage manager configured to manage one or more virtual namespaces; and a storage device controller configured to manage respective namespace associated with the one or more storage devices. The storage manager is further configured to expand a storage space associated with a virtual namespace on demand on the one or more local storage devices of the storage node at a request of the application running on the host computer when the storage node has a sufficient storage space.

Abstract: A circuit includes a programmable gain amplifier (PGA) having a PGA output. The circuit further includes a delta-sigma modulator having an input coupled to the PGA output. The circuit also includes a digital filter and a dynamic range enhancer (DRE) circuit. The digital filter is coupled to the delta-sigma modulator output. The DRE circuit is coupled to the delta-sigma modulator output and to the PGA. The DRE circuit is configured to monitor a signal level of the delta-sigma modulator output. Responsive to the signal level being less than a DRE threshold, the DRE circuit is configured to program the PGA for a gain level greater than unity gain and to cause the digital filter to implement an attenuation of a same magnitude as the gain level to be programmed into the PGA.

Abstract: A system includes: a reference buffer coupled to an input supply voltage; an analog-to-digital converter (ADC) coupled to an output of the reference buffer; and an output capacitor coupled between the output of the reference buffer and a ground node. The reference buffer includes: an integrator; an internal capacitor coupled between an output of the integrator and the ground node; a first gain stage with an input coupled to the output of the reference buffer; and a second gain stage with an input coupled to the output of the integrator. The output of the first gain stage is combined with the output of the integrator using a combine circuit.