Patents by Inventor Anandaroop Chakrabarti

Anandaroop Chakrabarti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10171031
    Abstract: An integrated electronic circuit is provided. The integrated electronic circuit includes a transconductance cell formed from transconductance cell devices. The integrated electronic circuit further includes active and passive decoupling circuits. The integrated electronic circuit also includes an oscillator having a tank that is direct current decoupled from the transconductance cell devices using the active and passive decoupling circuits to increase voltage swing and decrease phase noise of the oscillator.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anandaroop Chakrabarti, Mark Ferriss, Bodhisatwa Sadhu
  • Publication number: 20170317684
    Abstract: Circuits comprising: digital-to-amplitude converter (DAC), comprising: binary weighted switching transistors (BWSTs), each having gate coupled to amplitude control bit ACB, and wherein the drain of each of the BWSTs are connected together and wherein the source of each of the BWSTs are connected together; transistor M1 having gate coupled to input signal and first bias voltage BV1 and source coupled to the drains of the BWSTs; transistor M2 having gate coupled to BV2 and source coupled to the drain of M1; transistor M3 having gate coupled to BV3 and source coupled to the drain of M2; transistor having gate coupled to BV4, source coupled to the drain of M3; and inverter having input coupled to another ACB and having output coupled to the output of the DAC and the drain of M4.
    Type: Application
    Filed: January 9, 2017
    Publication date: November 2, 2017
    Applicant: The Trustees of Columbia University in the City of New York
    Inventors: Anandaroop Chakrabarti, Harish Krishnaswamy
  • Patent number: 9780725
    Abstract: An integrated electronic circuit is provided. The integrated electronic circuit includes a transconductance cell formed from transconductance cell devices. The integrated electronic circuit further includes active and passive decoupling circuits. The integrated electronic circuit also includes an oscillator having a tank that is direct current decoupled from the transconductance cell devices using the active and passive decoupling circuits to increase voltage swing and decrease phase noise of the oscillator.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: October 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Anandaroop Chakrabarti, Mark Ferriss, Bodhisatwa Sadhu
  • Publication number: 20170237397
    Abstract: An integrated electronic circuit is provided. The integrated electronic circuit includes a transconductance cell formed from transconductance cell devices. The integrated electronic circuit further includes active and passive decoupling circuits. The integrated electronic circuit also includes an oscillator having a tank that is direct current decoupled from the transconductance cell devices using the active and passive decoupling circuits to increase voltage swing and decrease phase noise of the oscillator.
    Type: Application
    Filed: May 1, 2017
    Publication date: August 17, 2017
    Inventors: Anandaroop Chakrabarti, Mark Ferriss, Bodhisatwa Sadhu
  • Publication number: 20170194920
    Abstract: In some embodiments, circuits for providing Class-E power amplifiers are provided, the circuits comprising: a first switch having a first side and a second side; a first Class-E load network coupled to the first side of the first switch; a second Class-E load network; and a second switch having a first side and a second side, the first side of the second switch being coupled the second side of the first switch and the second Class-E load network. In some embodiments, the circuits further comprise: a third switch having a first side and a second side; a third Class-E load network coupled to the first side of the third switch; a fourth Class-E load network; and a fourth switch having a first side and a second side, the first side of the fourth switch being coupled the second side of the third switch and the fourth Class-E load network.
    Type: Application
    Filed: August 29, 2016
    Publication date: July 6, 2017
    Applicant: The Trustees of Columbia University in the City of New York
    Inventors: Anandaroop Chakrabarti, Harish Krishnaswamy
  • Patent number: 9614541
    Abstract: Circuits comprising: digital-to-amplitude converter (DAC), comprising: binary weighted switching transistors (BWSTs), each having gate coupled to amplitude control bit ACB, and wherein the drain of each of the BWSTs are connected together and wherein the source of each of the BWSTs are connected together; transistor M1 having gate coupled to input signal and first bias voltage BV1 and source coupled to the drains of the BWSTs; transistor M2 having gate coupled to BV2 and source coupled to the drain of M1; transistor M3 having gate coupled to BV3 and source coupled to the drain of M2; transistor having gate coupled to BV4, source coupled to the drain of M3; and inverter having input coupled to another ACB and having output coupled to the output of the DAC and the drain of M4.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: April 4, 2017
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Anandaroop Chakrabarti, Harish Krishnaswamy
  • Publication number: 20170077871
    Abstract: An integrated electronic circuit is provided. The integrated electronic circuit includes a transconductance cell formed from transconductance cell devices. The integrated electronic circuit further includes active and passive decoupling circuits. The integrated electronic circuit also includes an oscillator having a tank that is direct current decoupled from the transconductance cell devices using the active and passive decoupling circuits to increase voltage swing and decrease phase noise of the oscillator.
    Type: Application
    Filed: November 2, 2016
    Publication date: March 16, 2017
    Inventors: Anandaroop Chakrabarti, Mark Ferriss, Bodhisatwa Sadhu
  • Publication number: 20170054434
    Abstract: An integrated electronic circuit is provided. The integrated electronic circuit includes a transconductance cell formed from transconductance cell devices. The integrated electronic circuit further includes active and passive decoupling circuits. The integrated electronic circuit also includes an oscillator having a tank that is direct current decoupled from the transconductance cell devices using the active and passive decoupling circuits to increase voltage swing and decrease phase noise of the oscillator.
    Type: Application
    Filed: August 21, 2015
    Publication date: February 23, 2017
    Inventors: Anandaroop Chakrabarti, Mark Ferriss, Bodhisatwa Sadhu
  • Patent number: 9559667
    Abstract: An integrated electronic circuit is provided. The integrated electronic circuit includes a transconductance cell formed from transconductance cell devices. The integrated electronic circuit further includes active and passive decoupling circuits. The integrated electronic circuit also includes an oscillator having a tank that is direct current decoupled from the transconductance cell devices using the active and passive decoupling circuits to increase voltage swing and decrease phase noise of the oscillator.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: January 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Anandaroop Chakrabarti, Mark Ferriss, Bodhisatwa Sadhu
  • Patent number: 9431975
    Abstract: In some embodiments, circuits for providing Class-E power amplifiers are provided, the circuits comprising: a first switch having a first side and a second side; a first Class-E load network coupled to the first side of the first switch; a second Class-E load network: and a second switch having a first side and a second side, the first side of the second switch being coupled the second side of the first switch and the second Class-E load network. In some embodiments, the circuits further comprise: a third switch having a first side and a second side; a third Class-E load network coupled to the first side of the third switch; a fourth Class-E load network; and a fourth switch having a first side and a second side, the first side of the fourth switch being coupled the second side of the third switch and the fourth Class-E load network.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: August 30, 2016
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Anandaroop Chakrabarti, Harish Krishnaswamy
  • Publication number: 20160099820
    Abstract: Circuits comprising: digital-to-amplitude converter (DAC), comprising: binary weighted switching transistors (BWSTs), each having gate coupled to amplitude control bit ACB, and wherein the drain of each of the BWSTs are connected together and wherein the source of each of the BWSTs are connected together; transistor M1 having gate coupled to input signal and first bias voltage BV1 and source coupled to the drains of the BWSTs; transistor M2 having gate coupled to BV2 and source coupled to the drain of M1; transistor M3 having gate coupled to BV3 and source coupled to the drain of M2; transistor having gate coupled to BV4, source coupled to the drain of M3; and inverter having input coupled to another ACB and having output coupled to the output of the DAC and the drain of M4.
    Type: Application
    Filed: October 1, 2015
    Publication date: April 7, 2016
    Inventors: Anandaroop Chakrabarti, Harish Krishnaswamy
  • Publication number: 20140028393
    Abstract: In some embodiments, circuits for providing Class-E power amplifiers are provided, the circuits comprising: a first switch having a first side and a second side; a first Class-E load network coupled to the first side of the first switch; a second Class-E load network: and a second switch having a first side and a second side, the first side of the second switch being coupled the second side of the first switch and the second Class-E load network. In some embodiments, the circuits further comprise: a third switch having a first side and a second side; a third Class-E load network coupled to the first side of the third switch; a fourth Class-E load network; and a fourth switch having a first side and a second side, the first side of the fourth switch being coupled the second side of the third switch and the fourth Class-E load network.
    Type: Application
    Filed: April 4, 2012
    Publication date: January 30, 2014
    Inventors: Anandaroop Chakrabarti, Harish Krishnaswamy