Abstract: A decoder includes a feature extraction circuit for calculating one or more feature vectors. An acoustic model circuit is coupled to receive one or more feature vectors from and assign one or more likelihood values to the one or more feature vectors. A memory architecture that utilizes on-chip state lattices and an off-chip memory for storing states of transition of the decoder is used to reduce reading and writing to the off-chip memory. The on-chip state lattice is populated with at least one of the states of transition stored in the off-chip memory. An on-chip word is generated from a snapshot from the on-chip state lattice. The on-chip state lattice and the on-chip word lattice act as an on-chip cache to reduce reading and writing to the off-chip memory.

Abstract: Systems and methods for implementing confidential communications between nodes of a network provide reduced power consumption, require less memory, and provide improved security, relative to previously-known systems and method. Preferred embodiments implement protocol functions in hardware, as opposed to software, to yield some or all of the foregoing improvements. Some embodiments use a hashing circuit for multiple purposes, while maintaining its ability to compute successive intermediate hash values. Some embodiments improve security of systems using circuits configured to leverage a favorable data format.

Abstract: Described is a lattice cryptography processor with configurable parameters. The lattice cryptography processor includes a sampling circuit configured to operate in accordance with a Secure Hash Algorithm 3 (SHA-3)-based pseudo-random number generator (PRNG), a single-port random access memory (RAM)-based number theoretic transform (NTT) memory architecture and a modular arithmetic unit. The described lattice cryptography processor is configured to be programmed with custom instructions for polynomial arithmetic and sampling. The configurable lattice cryptography processor may operate with lattice-based CCA-secure key encapsulation and a variety of different lattice-based protocols including, but not limited to: Frodo, NewHope, qTESLA, CRYSTALS-Kyber and CRYSTALS-Dilithium, achieving up to an order of magnitude improvement in performance and energy-efficiency compared to state-of-the-art hardware implementations.

Abstract: An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell.

Abstract: A decoder includes a feature extraction circuit for calculating one or more feature vectors. An acoustic model circuit is coupled to receive one or more feature vectors from and assign one or more likelihood values to the one or more feature vectors. A memory architecture that utilizes on-chip state lattices and an off-chip memory for storing states of transition of the decoder is used to reduce reading and writing to the off-chip memory. The on-chip state lattice is populated with at least one of the states of transition stored in the off-chip memory. An an on-chip word is generated from a snapshot from the on-chip state lattice. The on-chip state lattice and the on-chip word lattice act as an on-chip cache to reduce reading and writing to the off-chip memory.

Abstract: Systems and methods for implementing confidential communications between nodes of a network provide reduced power consumption, require less memory, and provide improved security, relative to previously-known systems and method. Preferred embodiments implement protocol functions in hardware, as opposed to software, to yield some or all of the foregoing improvements. Some embodiments use a hashing circuit for multiple purposes, while maintaining its ability to compute successive intermediate hash values. Some embodiments improve security of systems using circuits configured to leverage a favorable data format.

Abstract: A decoder comprises a feature extraction circuit for calculating one or more feature vectors; an acoustic model circuit coupled to receive one or more feature vectors from said feature extraction circuit and assign one or more likelihood values to the one or more feature vectors; a memory for storing states of transition of the decoder; and a search circuit for receiving an input from said acoustic model circuit corresponding to the one or more likelihood values based upon the one or more feature vectors, and for choosing states of transition from the memory based on the input from said acoustic model.

Abstract: Wireless resonant inductive power receivers for achieving detuning for a resonant wireless power transfer system including cooperative power sharing is described. Cooperative power sharing allows for detuning one or more wireless received coupled to a wireless charger to alter the power received at each wireless receiver.

Abstract: A method for assessing a three-dimensional (3D) surface area having one or more lesions is disclosed. The method includes steps of: capturing a two-dimensional (2D) color image and a depth image of the 3D surface area; enhancing contrast of the 2D color image; segmenting the one or more lesions of the 2D color image into one or more segmented lesions; and calculating 3D area of the one or more segmented lesions using information from 2D color image and the depth image.

Abstract: Described is a lattice cryptography processor with configurable parameters. The lattice cryptography processor includes a sampling circuit configured to operate in accordance with a Secure Hash Algorithm 3 (SHA-3)-based pseudo-random number generator (PRNG), a single-port random access memory (RAM)-based number theoretic transform (NTT) memory architecture and a modular arithmetic unit. The described lattice cryptography processor is configured to be programmed with custom instructions for polynomial arithmetic and sampling. The configurable lattice cryptography processor may operate with lattice-based CCA-secure key encapsulation and a variety of different lattice-based protocols including, but not limited to: Frodo, NewHope, qTESLA, CRYSTALS-Kyber and CRYSTALS-Dilithium, achieving up to an order of magnitude improvement in performance and energy-efficiency compared to state-of-the-art hardware implementations.

Abstract: A method and apparatus for achieving detuning for a resonant wireless power transfer system including cryptography is described. Detuning for a resonant wireless power transfer system including cryptography allows for detuning a wireless receiver based upon authentication between the wireless receiver and a wireless charger.

Abstract: Described is a receiver for improving end-to-end efficiency in a device-to-device wireless charging system using resonant energy transfer through an inductive link. The receiver includes an efficiency controller which dynamically tracks a maximum efficiency point and controls an impedance between an inductive coupling of the receiver and a receiver rectifier circuit such that an impedance seen by the inductive coupling is an impedance which maximizes (or nearly maximizes) efficiency of the inductively coupled wireless power transfer operation.

Abstract: Disclosed herein are novel devices comprising small, ultra-low power microelectronic components. In some instances, the microelectronic components is combined with a biosensor component that enables in situ detection of biomolecules. Also disclosed herein are methods of detecting signal analytes and methods of monitoring the health of a patient using these novel devices.

Abstract: Wireless resonant inductive power receivers for achieving detuning for a resonant wireless power transfer system including cooperative power sharing is described.

Abstract: A method and apparatus for achieving detuning for a resonant wireless power transfer system including cryptography is described. Detuning for a resonant wireless power transfer system including cryptography allows for detuning a wireless receiver based upon authentication between the wireless receiver and a wireless charger.

Abstract: A decoder comprises a feature extraction circuit for calculating one or more feature vectors; an acoustic model circuit coupled to receive one or more feature vectors from said feature extraction circuit and assign one or more likelihood values to the one or more feature vectors; a memory for storing states of transition of the decoder; and a search circuit for receiving an input from said acoustic model circuit corresponding to the one or more likelihood values based upon the one or more feature vectors, and for choosing states of transition from the memory based on the input from said acoustic model.

Abstract: A method for assessing a three-dimensional (3D) surface area having one or more lesions is disclosed. The method includes steps of: capturing a two-dimensional (2D) color image and a depth image of the 3D surface area; enhancing contrast of the 2D color image; segmenting the one or more lesions of the 2D color image into one or more segmented lesions; and calculating 3D area of the one or more segmented lesions using information from 2D color image and the depth image.

Abstract: An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell.

Abstract: Aspects disclosed in the detailed description include an ingestible power harvesting device and related applications. An ingestible power harvesting device includes a cathode electrode and an anode electrode that can catalyze a power generating reaction to generate a direct current (DC) power when surrounded by an acidic electrolyte. The cathode electrode and the anode electrode are coupled to an encapsulated electronic device that includes power harvesting circuitry configured to harvest the DC power and output a DC supply voltage for a prolonged period. In examples discussed herein, the prolonged period is at least five days. The DC supply voltage powers an electronic circuit in the encapsulated electronic device to support a defined in vivo operation (e.g., controlled drug delivery, in vivo vital signs monitoring, etc.). As such, the ingestible power harvesting device can operate in vivo for the prolonged period without requiring an embedded conventional battery.

Abstract: The present disclosure includes systems, methods, and computer-readable medium for monitoring and analyzing skin lesions. A sequence of images are be received, and color correction, contour detection, and feature detection are performed on the images. A progression factor is determined based on a comparison of the an area of the lesion between images. A system for monitoring a progression of a skin lesion is provided that includes a portable imaging device to aid in capturing images of the lesion, and a user device configured to analyze the images and determine a progression factor of the skin lesion.