Abstract: A novel doping technology for semiconductor wafers has been developed, referred to as a “quantum doping” process that permits the deposition of only a fixed, controlled number of atoms in the form of a monolayer in a substitutional condition where only unterminated surface bonds react with the dopant, thus depositing only a number of atoms equal to the atomic surface density of the substrate material. This technique results in providing a “quantized” set of possible dopant concentration values that depend only on the additional number of layers of substrate material formed over the single layer of dopant atoms.

Abstract: A novel doping technology for semiconductor wafers has been developed, referred to as a “quantum doping” process that permits the deposition of only a fixed, controlled number of atoms in the form of a monolayer in a substitutional condition where only unterminated surface bonds react with the dopant, thus depositing only a number of atoms equal to the atomic surface density of the substrate material. This technique results in providing a “quantized” set of possible dopant concentration values that depend only on the additional number of layers of substrate material formed over the single layer of dopant atoms.

Abstract: A novel doping technology for semiconductor wafers has been developed, referred to as a “quantum doping” process that permits the deposition of only a fixed, controlled number of atoms in the form of a monolayer in a substitutional condition where only unterminated surface bonds react with the dopant, thus depositing only a number of atoms equal to the atomic surface density of the substrate material. This technique results in providing a “quantized” set of possible dopant concentration values that depend only on the additional number of layers of substrate material formed over the single layer of dopant atoms.

Abstract: A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells. The semiconductor device also includes a redistribution layer electrically coupled to the plurality of LDMOS cells and a plurality of metallic pillars distributed over and electrically coupled to the redistribution layer.

Abstract: A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells, and a metallic layer electrically coupled to the plurality of LDMOS cells. The semiconductor device also includes a plurality of gate drivers positioned along a periphery of the semiconductor die and electrically coupled to gates of the plurality of LDMOS cells through the metallic layer.

Abstract: A semiconductor device and method of forming the same including, in one embodiment, a substrate and a plurality of source and drain regions formed as alternating pattern on the substrate. The semiconductor device also includes a plurality of gates formed over the substrate between and parallel to ones of the plurality of source and drain regions. The semiconductor device also includes a first plurality of alternating source and drain metallic strips formed in a first metallic layer above the substrate and parallel to and forming an electrical contact with respective ones of the plurality of source and drain regions.

Abstract: An apparatus and method of forming the same including, in one embodiment, a printed circuit board and a semiconductor device coupled to the printed circuit board. The apparatus also includes a decoupling device coupled to the printed circuit board and positioned under the semiconductor device.

Abstract: A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells, and a metallic layer electrically coupled to the plurality of LDMOS cells. The semiconductor device also includes a plurality of gate drivers positioned along a periphery of the semiconductor die and electrically coupled to gates of the plurality of LDMOS cells through the metallic layer.

Abstract: A semiconductor device and method of forming the same including, in one embodiment, a substrate and a plurality of source and drain regions formed as alternating pattern on the substrate. The semiconductor device also includes a plurality of gates formed over the substrate between and parallel to ones of the plurality of source and drain regions. The semiconductor device also includes a first plurality of alternating source and drain metallic strips formed in a first metallic layer above the substrate and parallel to and forming an electrical contact with respective ones of the plurality of source and drain regions.

Abstract: A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells. The semiconductor device also includes a redistribution layer electrically coupled to the plurality of LDMOS cells and a plurality of metallic pillars distributed over and electrically coupled to the redistribution layer.

Abstract: An extended work program (EWP) is provided in which unemployed and under-employed workers perform atomic units of work. The inventive system and method includes an administrative system, employer systems and participant systems, each of which communicates over the Internet. Employers locate EWP participants by querying an administrative system, which provides information regarding a pool of participants and further announces the available work to the pool. After suitable candidates are located, the administrative system, in conjunction with the employers' systems, trains, evaluates, and compensates EWP participants on an atomic unit of work basis. The participants communicate, in a human-centric trusted computing environment, with the employers through the administrative system.

Abstract: An extended work program (EWP) is provided in which unemployed and under-employed workers perform atomic units of work. The inventive system and method includes an administrative system, employer systems and participant systems, each of which communicates over the Internet. Employers locate EWP participants by querying an administrative system, which provides information regarding a pool of participants and further announces the available work to the pool. After suitable candidates are located, the administrative system, in conjunction with the employers' systems, trains, evaluates, and compensates EWP participants on an atomic unit of work basis. The participants communicate, in a human-centric trusted computing environment, with the employers through the administrative system.

Abstract: A method of manufacturing an integrated circuit and an integrated circuit employing the same. In one embodiment, the method of manufacturing the integrated circuit includes (1) conformally mapping a micromagnetic device, including a ferromagnetic core, to determine appropriate dimensions therefor, (2) depositing an adhesive over an insulator coupled to a substrate of the integrated circuit and (3) forming the ferromagnetic core of the appropriate dimensions over the adhesive.

Abstract: A method of manufacturing an integrated circuit and an integrated circuit employing the same. In one embodiment, the method of manufacturing the integrated circuit includes (1) conformally mapping a micromagnetic device, including a ferromagnetic core, to determine appropriate dimensions therefor, (2) depositing an adhesive over an insulator coupled to a substrate of the integrated circuit and (3) forming the ferromagnetic core of the appropriate dimensions over the adhesive.

Abstract: A method of manufacturing an integrated circuit and an integrated circuit employing the same. In one embodiment, the method of manufacturing the integrated circuit includes (1) conformally mapping a micromagnetic device, including a ferromagnetic core, to determine appropriate dimensions therefor, (2) depositing an adhesive over an insulator coupled to a substrate of the integrated circuit and (3) forming the ferromagnetic core of the appropriate dimensions over the adhesive.

Abstract: A programmable controller for switch-mode power converters that operates in a digital domain without reliance on operation software and the ability to vastly reduce or eliminate analog circuitry. The digital controller is re-programmable. In one embodiment, the substantially digital portion of the controller is a Field Programmable Gate Array that controls operation of the converter by generally converting an analog reference signal(s) (e.g. the voltage output) into the digital domain. The controller then can perform distributed arithmetic to generate a square wave signal capable of controlling at least a main switch of the converter. The present invention can, if desired, essentially eliminate analog controllers in power conversion systems such as switch-mode converters.

Abstract: A silicon-on-silicon dual MCM apparatus comprising a printed circuit board having a voltage isolation boundary contained therein supporting a pair of multi-chip modules on either side of the voltage isolation boundary. The MCMs safely convey signals across the isolation boundary via discrete optical coupling means or the like. The optical coupling means allow safe and efficient conveyance of signals across the voltage isolation boundary enabling a designer to group high voltage components on one side of the boundary and low voltage components on the other side of the boundary. This obviates to a degree the need for multi-layered PCBs. A relatively large number of passive components (resistors and capacitors) are integrated into a silicon substrate with flip-chip analog integrated circuits (ICs). Operational characteristics of the controller are verified after integration and are compared to the discrete version.

Abstract: Expedient fabrication of fine-featured integrated circuits entails aperture pattern delineation to produce a masking layer atop a semiconductor body followed by insertion within a controlled atmosphere chamber within which device-functional layered material is epitaxially grown within apertures. Critical, device-consequential properties of epitaxial material is assured by removal of a thin surface layer of material revealed during delineation. Such removal, sufficient to eliminate meaningful contamination and/or crystalline damage introduced during delineation, is of sufficiently small quantity as to be accommodated within the chamber. Under most circumstances, the controlled atmosphere is at reduced pressure as required for e.g. MOMBE epitaxial growth.

Abstract: A process for growing selective epitaxial layers on a silicon substrate. In a epitaxial growth reactor, hydrogen and the reactive gasses, the silicon source gas and hydrochloric acid, are introduced. The amount of silicon to free hydrochloric acid is controlled to be about 1:6 during the growth process and then turned off, the hydrogen remaining on. The resulting epitaxial layer may be grown over one micron in thickness with less than 0.1 micron of faceting. Further, a etchant of H.sub.2 O and HF diluted in NHO.sub.3 is first used to remove surface damage on the silicon substrate prior to epitaxial layer growth.

Abstract: A dielectrically-isolated structure and method of fabricating the same is disclosed wherein the structure includes a layer of silicide which is selectively doped, preferably using an ion implantation process. The doped silicide is then used as the diffusion source for the subsequent formation (through a heat treatment) of various active portions (collector, emitter, drain, source, for example) of a variety of high-voltage, high-speed active devices. The non-doped silicide is advantageously utilized as a low-resistance contact between the buried diffusion region and the surface electrode.