Abstract: A method of removing natural oxides and other contaminants on silicon or polysilicon and then depositing polysilicon thereon. The natural oxide is substantially removed from the exposed silicon with an anhydrous etchant and then the polysilicon is deposited on the exposed silicon. The etching and depositing steps occur in the same reactor chamber (in-situ). A portion of the end of the selective etching step overlaps with a portion of the beginning of the polysilicon deposition step to achieve an interface between the underlying silicon and the deposited polysilicon that is substantially free of native oxides and other contaminants.

Abstract: A high performance bipolar transistor structure is disclosed which exhibits an extremely low extrinsic base resistance by virtue of a silicide layer which is included in the base contact portion of the structure. The silicide layer is situated to be electrically in parallel with the conventional heavily-doped polysilicon base contact region, where a vertical polysilicon runner is used to provide a self-aligned electrical contact to the base. The parallel combination of the low resistivity (0.5-4 ohm/square) silicide with the polysilicon (sheet resistance of 10-100 ohm/square) results in a low extrinsic base resistance on the order of 0.5-4 ohm/square. The disclosed device also includes a submicron emitter size, defined by vertical oxide sidewalls above the base region, which further improves the high frequency performance of the device.

Abstract: A method of fabricating a dielectrically-isolated structure is disclosed rein the structure includes a layer of silicide which is selectively doped, preferably using an ion implantation process. The doped silicide is then used as the diffusion source for the subsequent formation (through a heat treatment) of various active portions (collector, emitter, drain, source, for example) of a variety of high-voltage, high-speed active devices. The non-doped silicide is advantageously utilized as a low-resistance contact between the buried diffusion region and the surface electrode. In an alternative embodiment, bottom portions of the silicide contiguous to the tub are removed, leaving only vertical silicide portions adjacent to the sidewalls of the dielectrically isolated tub.

Abstract: Submicron resolution in the fabrication of transistors is obtained by using sidewall techniques. The techniques described remove the sidewalls after oxidizing the materials between the sidewalls and the openings so formed by the removal are used as a mask for subsequent substrate modification by either diffusion or ion implantation.

Abstract: A method of fabricating bipolar intergratable transistors includes a recrystallization step. A monocrystalline epitaxial layer is deposited upon a highly doped substrate and impurities are introduced into a portion of the epitaxial layer to form a first transistor region. A polysilicon layer is deposited upon the surface and a portion of the polycrystalline layer is recrystallized wherein the first transistor region serves as a seed. Impurities are introduced into the recrystallized portion to form a base. An additional polysilicon layer is deposited over the substrate and a portion is recrystallized wherein the base serves as a seed. A second transistor region is formed in the recrystallized portion of the additional polysilicon layer.

Abstract: A method of fabricating bipolar integratable transistors includes a recrystallization step. A monocrystalline epitaxial layer is deposited upon a highly doped substrate and impurities are introduced into a portion of the epitaxial layer to form a first transistor region. A polysilicon layer is deposited upon the surface and a portion of the polycrystalline layer is recrystallized wherein the first transistor region serves as a seed. Impurities are introduced into the recrystallized portion to form a base. An additional polysilicon layer is deposited over the substrate and a portion is recrystallized wherein the base serves as a seed. A second transistor region is formed in the recrystallized portion of the additional polysilicon layer.

Abstract: A new sub-micron bipolar transistor structure is proposed which utilizes narrow horizontal conducting layers between the edges of the active areas and the associated metal contacts. This structure allows the formation of a completely vertical transistor structure and eliminates the need for the extended buried collector and collector reach-through diffusion regions.