Patents by Inventor Anbang Yao

Anbang Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230359873
    Abstract: Methods and apparatus for discrimitive semantic transfer and physics-inspired optimization in deep learning are disclosed. A computation training method for a convolutional neural network (CNN) includes receiving a sequence of training images in the CNN of a first stage to describe objects of a cluttered scene as a semantic segmentation mask. The semantic segmentation mask is received in a semantic segmentation network of a second stage to produce semantic features. Using weights from the first stage as feature extractors and weights from the second stage as classifiers, edges of the cluttered scene are identified using the semantic features.
    Type: Application
    Filed: May 3, 2023
    Publication date: November 9, 2023
    Inventors: Anbang YAO, Hao ZHAO, Ming LU, Yiwen GUO, Yurong CHEN
  • Publication number: 20230359461
    Abstract: One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a one-bit weight associated with a neural network, as well as an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a fused operation including an exclusive not OR (XNOR) operation and a population count operation. The adder is configured to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.
    Type: Application
    Filed: May 11, 2023
    Publication date: November 9, 2023
    Applicant: Intel Corporation
    Inventors: Kevin Nealis, Anbang Yao, Xiaoming Chen, Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Eriko Nurvitadhi, Balaji Vembu, Nicolas C. Galoppo Von Borries, Rajkishore Barik, Tsung-Han Lin, Kamal Sinha
  • Patent number: 11803739
    Abstract: Methods and systems for budgeted and simplified training of deep neural networks (DNNs) are disclosed. In one example, a trainer is to train a DNN using a plurality of training sub-images derived from a down-sampled training image. A tester is to test the trained DNN using a plurality of testing sub-images derived from a down-sampled testing image. In another example, in a recurrent deep Q-network (RDQN) having a local attention mechanism located between a convolutional neural network (CNN) and a long-short time memory (LSTM), a plurality of feature maps are generated by the CNN from an input image. Hard-attention is applied by the local attention mechanism to the generated plurality of feature maps by selecting a subset of the generated feature maps. Soft attention is applied by the local attention mechanism to the selected subset of generated feature maps by providing weights to the selected subset of generated feature maps in obtaining weighted feature maps.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: October 31, 2023
    Assignee: Intel Corporation
    Inventors: Yiwen Guo, Yuqing Hou, Anbang Yao, Dongqi Cai, Lin Xu, Ping Hu, Shandong Wang, Wenhua Cheng, Yurong Chen, Libin Wang
  • Publication number: 20230343068
    Abstract: Techniques related to implementing and training image classification networks are discussed. Such techniques include applying shared convolutional layers to input images regardless of resolution and applying normalization selectively based on the input image resolution. Such techniques further include training using mixed image size parallel training and mixed image size ensemble distillation.
    Type: Application
    Filed: June 15, 2020
    Publication date: October 26, 2023
    Applicant: Intel Corporation
    Inventors: Anbang YAO, Yikai WANG, Ming LU, Shandong WANG, Feng CHEN
  • Patent number: 11797837
    Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: October 24, 2023
    Assignee: Intel Corporation
    Inventors: Altug Koker, Abhishek R. Appu, Kamal Sinha, Joydeep Ray, Balaji Vembu, Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Anbang Yao, Kevin Nealis, Xiaoming Chen, John C. Weast, Justin E. Gottschlich, Prasoonkumar Surti, Chandrasekaran Sakthivel, Farshad Akhbari, Nadathur Rajagopalan Satish, Liwei Ma, Jeremy Bottleson, Eriko Nurvitadhi, Travis T. Schluessler, Ankur N. Shah, Jonathan Kennedy, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Publication number: 20230334316
    Abstract: Described herein is a graphics processor comprising a memory device and a graphics processing cluster coupled with the memory device. The graphics processing cluster includes a plurality of graphics multiprocessors interconnected via a data interconnect. A graphics multiprocessor includes circuitry configured to load a modular neural network including a plurality of subnetworks, each of the plurality of subnetworks trained to perform a computer vision operation on a separate subject.
    Type: Application
    Filed: May 9, 2023
    Publication date: October 19, 2023
    Applicant: Intel Corporation
    Inventors: Altug Koker, Abhishek R. Appu, Kamal Sinha, Joydeep Ray, Balaji Vembu, Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Anbang Yao, Kevin Nealis, Xiaoming Chen, John C. Weast, Justin E. Gottschlich, Prasoonkumar Surti, Chandrasekaran Sakthivel, Farshad Akhbari, Nadathur Rajagopalan Satish, Liwei Ma, Jeremy Bottleson, Eriko Nurvitadhi, Travis T. Schluessler, Ankur N. Shah, Jonathan Kennedy, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Patent number: 11790223
    Abstract: Methods and systems are disclosed for boosting deep neural networks for deep learning. In one example, in a deep neural network including a first shallow network and a second shallow network, a first training sample is processed by the first shallow network using equal weights. A loss for the first shallow network is determined based on the processed training sample using equal weights. Weights for the second shallow network are adjusted based on the determined loss for the first shallow network. A second training sample is processed by the second shallow network using the adjusted weights. In another example, in a deep neural network including a first weak network and a second weak network, a first subset of training samples is processed by the first weak network using initialized weights. A classification error for the first weak network on the first subset of training samples is determined.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: October 17, 2023
    Assignee: Intel Corporation
    Inventors: Libin Wang, Yiwen Guo, Anbang Yao, Dongqi Cai, Lin Xu, Ping Hu, Shandong Wang, Wenhua Cheng, Yurong Chen
  • Patent number: 11790631
    Abstract: An example apparatus for mining multi-scale hard examples includes a convolutional neural network to receive a mini-batch of sample candidates and generate basic feature maps. The apparatus also includes a feature extractor and combiner to generate concatenated feature maps based on the basic feature maps and extract the concatenated feature maps for each of a plurality of received candidate boxes. The apparatus further includes a sample scorer and miner to score the candidate samples with multi-task loss scores and select candidate samples with multi-task loss scores exceeding a threshold score.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: October 17, 2023
    Assignee: Intel Corporation
    Inventors: Anbang Yao, Yun Ren, Hao Zhao, Tao Kong, Yurong Chen
  • Publication number: 20230315481
    Abstract: Described herein is a general-purpose graphics processing unit including a multiprocessor having a single instruction, multiple thread, SIMT, architecture. The multiprocessor comprises multiple sets of compute units each having a first logic unit configured to perform floating-point operations and a second logic unit configured to perform integer operations, with a thread of the floating-point instruction being executed in parallel with a thread of the integer instruction.
    Type: Application
    Filed: May 4, 2023
    Publication date: October 5, 2023
    Applicant: Intel Corporation
    Inventors: ELMOUSTAPHA OULD-AHMED-VALL, BARATH LAKSHMANAN, TATIANA SHPEISMAN, Joydeep Ray, Ping T. Tang, Michael Strickland, Xiaoming Chen, Anbang Yao, Ben J. Ashbaugh, Linda L. Hurd, Liwei Ma
  • Publication number: 20230298204
    Abstract: Apparatus and methods for three-dimensional pose estimation are disclosed herein. An example apparatus includes an image synchronizer to synchronize a first image generated by a first image capture device and a second image generated by a second image capture device, the first image and the second image including a subject; a two-dimensional pose detector to predict first positions of keypoints of the subject based on the first image and by executing a first neural network model to generate first two-dimensional data and predict second positions of the keypoints based on the second image and by executing the first neural network model to generate second two-dimensional data; and a three-dimensional pose calculator to generate a three-dimensional graphical model representing a pose of the subject in the first image and the second image based on the first two-dimensional data, the second two-dimensional data, and by executing a second neural network model.
    Type: Application
    Filed: June 26, 2020
    Publication date: September 21, 2023
    Inventors: Shandong Wang, Yangyuxuan Kang, Anbang Yao, Ming Lu, Yurong Chen
  • Publication number: 20230290134
    Abstract: A method and system of multiple facial attributes recognition using highly efficient neural networks.
    Type: Application
    Filed: September 25, 2020
    Publication date: September 14, 2023
    Applicant: Intel Corporation
    Inventors: Ping Hu, Anbang Yao, Xiaolong Liu, Yurong Chen, Dongqi Cai
  • Patent number: 11748606
    Abstract: In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: September 5, 2023
    Assignee: INTEL CORPORATION
    Inventors: Kamal Sinha, Balaji Vembu, Eriko Nurvitadhi, Nicolas C. Galoppo Von Borries, Rajkishore Barik, Tsung-Han Lin, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Farshad Akhbari, Narayan Srinivasa, Feng Chen, Dukhwan Kim, Nadathur Rajagopalan Satish, John C. Weast, Mike B. MacPherson, Linda L. Hurd, Vasanth Ranganathan, Sanjeev S. Jahagirdar
  • Publication number: 20230274580
    Abstract: A method and system of image processing for action classification uses fine-grained motion-attributes.
    Type: Application
    Filed: August 14, 2020
    Publication date: August 31, 2023
    Applicant: Intel Corporation
    Inventors: Anbang YAO, Shandong WANG, Ming LU, Yuqing HOU, Yangyuxuan KANG, Yurong CHEN
  • Publication number: 20230274132
    Abstract: Methods, apparatus, systems, and articles of manufacture to dynamically normalize data in neural networks are disclosed. An apparatus for use with a machine learning model includes at least one normalization calculator to generate a plurality of alternate normalized outputs associated with input data for the machine learning model. Different ones of the alternate normalized outputs based on different normalization techniques. The apparatus further includes a soft weighting engine to generate a plurality of soft weights based on the input data. The apparatus also includes a normalized output generator to generate a final normalized output based on the plurality of alternate normalized outputs and the plurality of soft weights.
    Type: Application
    Filed: August 26, 2020
    Publication date: August 31, 2023
    Inventors: Dongqi Cai, Anbang Yao, Yurong Chen
  • Patent number: 11727527
    Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex compute operation.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: August 15, 2023
    Assignee: Intel Corporation
    Inventors: Eriko Nurvitadhi, Balaji Vembu, Nicolas C. Galoppo Von Borries, Rajkishore Barik, Tsung-Han Lin, Kamal Sinha, Nadathur Rajagopalan Satish, Jeremy Bottleson, Farshad Akhbari, Altug Koker, Narayan Srinivasa, Dukhwan Kim, Sara S. Baghsorkhi, Justin E. Gottschlich, Feng Chen, Elmoustapha Ould-Ahmed-Vall, Kevin Nealis, Xiaoming Chen, Anbang Yao
  • Patent number: 11727246
    Abstract: Embodiments provide systems and methods which facilitate optimization of a convolutional neural network (CNN). One embodiment provides for a non-transitory machine-readable medium storing instructions that cause one or more processors to perform operations comprising processing a trained convolutional neural network (CNN) to generate a processed CNN, the trained CNN having weights in a floating-point format. Processing the trained CNN includes quantizing the weights in the floating-point format to generate weights in an integer format. Quantizing the weights includes generating a quantization table to enable non-uniform quantization of the weights and quantizing the weights from the floating-point format to the integer format using the quantization table. The operations additionally comprise performing an inference operation utilizing the processed CNN with the integer format weights.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 15, 2023
    Assignee: Intel Corporation
    Inventors: Liwei Ma, Elmoustapha Ould-Ahmed-Vall, Barath Lakshmanan, Ben J. Ashbaugh, Jingyi Jin, Jeremy Bottleson, Mike B. Macpherson, Kevin Nealis, Dhawal Srivastava, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman, Altug Koker, Abhishek R. Appu
  • Patent number: 11720355
    Abstract: One embodiment provides a graphics processor comprising a memory controller and a graphics processing resource coupled with the memory controller. The graphics processing resource includes circuitry configured to execute an instruction to perform a matrix operation on first input including weight data and second input including input activation data, generate intermediate data based on a result of the matrix operation, quantize the intermediate data to a floating-point format determined based on a statistical distribution of first output data, and output, as second output data, quantized intermediate data in a determined floating-point format.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: August 8, 2023
    Assignee: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Patent number: 11704569
    Abstract: Methods and apparatus are disclosed for enhancing a binary weight neural network using a dependency tree. A method of enhancing a convolutional neural network (CNN) having binary weights includes constructing a tree for obtained binary tensors, the tree having a plurality of nodes beginning with a root node in each layer of the CNN. A convolution is calculated of an input feature map with an input binary tensor at the root node of the tree. A next node is searched from the root node of the tree and a convolution is calculated at the next node using a previous convolution result calculated at the root node of the tree. The searching of a next node from root node is repeated for all nodes from the root node of the tree, and a convolution is calculated at each next node using a previous convolution result.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: July 18, 2023
    Assignee: Intel Corporation
    Inventors: Yiwen Guo, Anbang Yao, Hao Zhao, Ming Lu, Yurong Chen
  • Patent number: 11704894
    Abstract: An example apparatus for semantic image segmentation includes a receiver to receive an image to be segmented. The apparatus also includes a gated dense pyramid network including a plurality of gated dense pyramid (GDP) blocks to be trained to generate semantic labels for respective pixels in the received image. The apparatus further includes a generator to generate a segmented image based on the generated semantic labels.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: July 18, 2023
    Assignee: Intel Corporation
    Inventors: Libin Wang, Anbang Yao, Jianguo Li, Yurong Chen
  • Patent number: 11693658
    Abstract: One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a ternary weight associated with a neural network and an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input based on the ternary weight to generate an intermediate product and the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: July 4, 2023
    Assignee: Intel Corporation
    Inventors: Kevin Nealis, Anbang Yao, Xiaoming Chen, Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Eriko Nurvitadhi, Balaji Vembu, Nicolas C. Galoppo Von Borries, Rajkishore Barik, Tsung-Han Lin, Kamal Sinha