Abstract: A system and method is disclosed for providing a low voltage high density multi-bit storage flash memory. A dual bit memory cell of the invention comprises a substrate having a common source, a first drain and first channel, and a second drain and a second channel. A common control gate is located above the source. A first floating gate and a second floating gate are located on opposite sides of the control gate. Each floating gate is formed with a sharp tip adjacent to the control gate and an upper curved surface that follows a contour of the surface of the control gate. The sharp tips of the floating gates efficiently discharge electrons into the control gate when the memory cell is erased. The curved surfaces increase capacitor coupling between the control gate and the floating gates.

Abstract: A system and method is disclosed for providing a low voltage high density multi-bit storage flash memory. A dual bit memory cell of the invention comprises a substrate having a common source, a first drain and first channel, and a second drain and a second channel. A common control gate is located above the source. A first floating gate and a second floating gate are located on opposite sides of the control gate. Each floating gate is formed with a sharp tip adjacent to the control gate and an upper curved surface that follows a contour of the surface of the control gate. The sharp tips of the floating gates efficiently discharge electrons into the control gate when the memory cell is erased. The curved surfaces increase capacitor coupling between the control gate and the floating gates.

Abstract: A system and method is disclosed for providing a low voltage high density multi-bit storage flash memory. A dual bit memory cell of the invention comprises a substrate having a common source, a first drain and first channel, and a second drain and a second channel. A common control gate is located above the source. A first floating gate and a second floating gate are located on opposite sides of the control gate. Each floating gate is formed with a sharp tip adjacent to the control gate and an upper curved surface that follows a contour of the surface of the control gate. The sharp tips of the floating gates efficiently discharge electrons into the control gate when the memory cell is erased. The curved surfaces increase capacitor coupling between the control gate and the floating gates.

Abstract: A structure for decreasing minimum feature size in an integrated circuit design that includes a substrate comprising a first material is provided. The structure comprises a layer of second material formed on a surface of the substrate and a micro-aperture formed in the layer of second material. The micro-aperture has sidewalls formed to be substantially perpendicular to the surface of the substrate and a horizontal tip formed on the surface of the substrate and extending orthogonally from a portion of the sidewalls.

Abstract: A method for creating graded or tapered dopant profiles in a semiconductor layer or layers. Preferably, a sub-micron horizontal tip feature is used to control the doping of the layer beneath the feature.

Abstract: A single, controlled etch step can be used to form a sharp tip feature along a sidewall of an etch feature. An etch process is used that is selective to a layer of tip material relative to the substrate upon which the layer is deposited. A lag can be created in the etch, such that the etch rate is slower near the sidewall. The sharp tip feature is formed from the same layer of material used to create the etch feature. The sharp tip feature can be used to decrease the minimum critical dimension of an etch process, such as may be due to the minimum resolution of a photolithographic process. The novel tip feature also can be used for other applications, such as to create a microaperture for a photosensitive device, or to create a micromold that can be used to form objects such as microlenses.