STRUCTURE FOR DECREASING MINIMUM FEATURE SIZE IN AN INTEGRATED CIRCUIT
A structure for decreasing minimum feature size in an integrated circuit design that includes a substrate comprising a first material is provided. The structure comprises a layer of second material formed on a surface of the substrate and a micro-aperture formed in the layer of second material. The micro-aperture has sidewalls formed to be substantially perpendicular to the surface of the substrate and a horizontal tip formed on the surface of the substrate and extending orthogonally from a portion of the sidewalls.
The present application is a divisional of co-pending and commonly-assigned application Ser. No. 11/592,800, filed on Nov. 3, 2006, which is a divisional of application Ser. No. 10/726,122, filed on Dec. 2, 2003, now U.S. Pat. No. 7,175,777, which issued on Feb. 13, 2007.
TECHNICAL FIELD OF THE INVENTIONThe present invention is directed to techniques for decreasing minimum feature size in integrated circuit structures.
SUMMARYEmbodiments of the invention a structure for decreasing minimum feature size in an integrated circuit design that includes a substrate comprising a first material. The structure comprises a layer of second material formed on a surface of the substrate and a micro-aperture formed in the layer of second material. The micro-aperture has sidewalls formed to be substantially perpendicular to the surface of the substrate and a horizontal tip formed on the surface of the substrate and extending orthogonally from a portion of the sidewalls.
The features and advantages of the various aspects of the present invention will be more fully understood and appreciated upon consideration of the following detailed description of invention and the accompanying drawings, which set forth illustrative embodiments in which the concepts of the invention are utilized.
As performance requirements for various semiconductor devices increase, the need for higher density designs requires the creation of features having dimensions that extend down to the micron and submicron level. Many designs are limited by physical constraints, as minimum features sizes are constrained by current processing technology. For example, feature sizes can be limited by the resolution of a photolithography process, or the minimum feature size of a circuit design that is capable of being transferred to a photoresist mask.
Systems and methods in accordance with various embodiments of the present invention can overcome these and other deficiencies in existing etch processes in order to significantly reduce the minimum dimension of features that can be created by such an etch process. A novel etch process can be used to create two distinct features from a single etch step. For example,
If properly selected and controlled, a RIE process can have a much slower etch rate near a vertical edge of a material being etched than in a large horizontal area. Careful control of the etch can result in the formation of a sharp horizontal feature 210 as shown in
As discussed above, the use of such a process to create a tip feature can increase the effective resolution of a lithographic process. For example,
The ability to manufacture such horizontal tip features arises from the fact that the etch of a film or layer in certain processes tends to go slower near an edge, such as an edge of a tip material layer located adjacent to an edge of a photoresist layer. A polymer buildup can occur near the resist sidewall during the etch, as is known in the art. Sidewall polymerization is typically used to control the profile, aspect ratio, or taper of a sidewall during etch. Processes in accordance with embodiments of the present invention can not only control the profile or taper of a vertical sidewall, but can also create a separate horizontal feature from the same etch step. The polymer buildup, if properly controlled, can cause the etch to not only proceed more slowly along the edge than elsewhere, but can also progress with a desired rate relative to the bulk etch such that a pre-determined etch lag is purposefully created. If the etch is halted in the appropriate location, or at the appropriate time, the etch will have cleared out the film or layer away from the edge, leaving a substantially vertical sidewall and a residual tip feature. The timing and precision of the process can be controlled using various process parameters, such as the rate of polymer generation and the etch chemistry.
While any appropriate etch technique can be used, it can be preferable in some embodiments to utilize a Reactive Ion Etch (RIE) process. The process parameters can include any appropriate parameters known in the art for the chemistry and materials of the etch process, as well as for the shape/size of the feature(s) to be created by the etch process. Etch process gases can include any appropriate process gases, such as but not limited to O2, CF4, SF6, CHF3, He, N2, Ar, Cl2, Ar, and SiCl4. Etch rates will vary depending on the gases and material(s) being etched, but often are in the range of from tens of nanometers to microns per minute. The pressure in an etch chamber can be any appropriate pressure, including but not limited to pressures on the order of 50 mTorr to 100 mTorr, or on the order of 0 mTorr to about 1000 mTorr, for example. The power setting for an RF supply can be any appropriate setting, including but not limited to powers on the order of about 100 W to about 600 W, or on the order of about 50 W to about 1500 W. Once the process gases, materials, and feature sizes have been determined, the process parameters can be adjusted to appropriately set the etch progression in the bulk and along the sidewalls.
In certain embodiments, it is necessary to properly end the etch process. While numerous ways exist to determine when to end the etch, two relatively simple examples include timing and endpoint approaches. In a timing approach, knowing the etch rate and thickness of the tip material, as well as the desired tip feature size, can allow for a determination of the length of time necessary to expose the tip material to the etch. The etch process can then be stopped after the determined period of time passes. In a second exemplary approach, which can be less dependent upon process variation in some embodiments, an endpoint can be utilized to properly end the etch. After the etch process reaches the substrate, a signal can be generated to measure the width of the open area in the tip material and/or the position of the receding edge of the tip material during the etch. The etch process can be stopped once the etch, or the edge of the tip material, reaches the desired tip position. It may be necessary to stop the etch process slightly before the etch reaches the desired position, in order to avoid inadvertent overetch.
Horizontal tip features can be formed in any of a number of geometries, as shown for example in
The tip material used in the above examples can be any appropriate material, such as for example a nitride material, such as silicon nitride, or polysilicon. The substrate material can be any appropriate material, different than that of the tip material, such as for example single crystal silicon or polysilicon. The layer thickness of the tip material and substrate can be any appropriate thickness, except that the thickness of the tip material layer is preferably at least as great as the desired height of the horizontal tip feature at the base of the tip. The height and length of the tip can be dependent upon the process parameters and materials used, but in some embodiments are on the order of about 1.0 microns. The ratio of tip height to tip length can vary, and can be controlled or determined by the parameters of the etch process. Depending upon the precision and controllability of the etch process and the materials selected, tips with dimensions less than one micron can also be formed.
The etch process used, such as a reactive ion etch (RIE) process, should be selective to the tip material relative to the substrate. The etch can have additional etch steps in some embodiments, although only one etch step is necessary in most embodiments. Any etch process having an appropriate chemistry can be selected, as long as the etch process exhibits a lag, or lower etch rate, near a sidewall or substantially vertical feature. The etch process should be terminated at the appropriate point in the etch, prior to completion of a high-aspect ratio feature and/or a clearing of the tip material. Such a process can also be used on materials such as thin films to form extremely sharp features.
As shown in
It should be recognized that a number of variations of the above-identified embodiments will be obvious to one of ordinary skill in the art in view of the foregoing description. Accordingly, the invention is not to be limited by those specific embodiments and methods of the present invention shown and described herein. Rather, the scope of the invention is to be defined by the following claims and their equivalents.
Claims
1. A structure for decreasing minimum feature size in an integrated circuit design that includes a substrate comprising a first material, the structure comprising:
- a layer of second material formed on a surface of the substrate; and
- a micro-aperture formed in the layer of second material, the micro-aperture having sidewalls formed to be substantially perpendicular to the surface of the substrate and a horizontal tip formed on the surface of the substrate and extending orthogonally from a portion of the sidewalls.
2. The structure of claim 1, wherein the horizontal tip defines an exposed portion of the surface of the substrate.
3. The structure of claim 1, wherein the first material is different than the second material.
4. The structure of claim 1, wherein the first material comprises single crystal silicon.
5. The structure of claim 1, wherein the first material comprises polysilicon.
6. The structure of claim 1, wherein the second material comprises a nitride.
7. The structure of claim 6, wherein the nitride comprises silicon nitride.
8. The structure of claim 1, wherein the second material comprises polysilicon.
9. The structure of claim 1, wherein the horizontal tip defines a substantially circular exposed portion of the surface of the substrate.
10. The structure of claim 1, wherein the horizontal tip defines an exposed portion of the surface of the substrate, and further comprising:
- a photosensitive device formed in the exposed portion of the surface of the substrate.
11. The structure of claim 9, wherein the exposed portion of the surface of the substrate is substantially circular.
12. The structure of claim 1, wherein the horizontal tip defines an exposed portion of the surface of the substrate, and further comprising;
- a microscale lens formed in the exposed portion of the surface of the substrate.
13. The structure of claim 11, wherein the exposed portion of the surface of the substrate is substantially circular.
Type: Application
Filed: Jan 13, 2011
Publication Date: May 19, 2011
Inventors: André Paul Labonté (Lewiston, ME), Lee James Jacobson (Cape Elizabeth, ME)
Application Number: 13/005,767
International Classification: H01L 31/0232 (20060101);