Patents by Inventor Andre Cote

Andre Cote has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070098942
    Abstract: A poly sheet continuously moving in a machine direction is heated to a temperature just below its glass thermal temperature to make the poly malleable. A circuit (e.g., RFID chip, EAS chip, transponder, IC) is placed on the poly sheet and embedded into the poly sheet, preferably with a heat resistant soft (e.g., rubber) roller that presses the circuit into the poly without breaking the circuit. A conductive strip or wire may be applied on or into the poly sheet to align with connection points (e.g., conductive bumps) of the circuit for conductive communication with the circuit. The conductive strip or wire is preferably cut to form gaps that are nonconductive between the cut sections of wire to avoid shorting of the circuit and/or allow the conductive strip or wire to function as an antenna for the circuit, and thus to form a chip strap or tag. The poly sheet thus provides a protective womb or shield for the circuit and wire.
    Type: Application
    Filed: October 30, 2006
    Publication date: May 3, 2007
    Applicant: CHECKPOINT SYSTEMS, INC.
    Inventors: Andre Cote, Detlef Duschek
  • Publication number: 20070090955
    Abstract: A capacitor strap that is applied to a security tag coil or antenna to form and properly tune an EAS or an RFID security tag. The capacitor strap is a thin film capacitor formed of two metal foils in between which is a dielectric material having ends that are electrically coupled to different points of a security tag coil or antenna. The capacitor strap may include an RFID integrated circuit, either in series or in parallel with the capacitor, which is then applied to security tag coil at a particular location to tune the tag to a predetermined frequency.
    Type: Application
    Filed: October 10, 2006
    Publication date: April 26, 2007
    Applicant: CHECKPOINT SYSTEMS, INC.
    Inventors: Andre Cote, Luis Soler Bonnin
  • Publication number: 20070018824
    Abstract: A method for installing an RFID tag on shipping articles includes applying a strip of conductive material to the surface of the article and providing an RFID chip having a body, a first bottom conductive point, a second bottom conductive point and a nonconductive fin between the first bottom conductive point and the second bottom conductive point. The fin is received in the shipping article. The RFID chip is attached to the shipping article by inserting the chip onto the strip of conductive material on the shipping article such that the fin severs the strip into a first strip and a second strip. The first bottom conductive point is electrically attached to the first strip and the second bottom conductive point is electrically attached to the second strip.
    Type: Application
    Filed: July 17, 2006
    Publication date: January 25, 2007
    Applicant: Checkpoint Systems, Inc.
    Inventors: Thomas Clare, Andre Cote
  • Publication number: 20070012775
    Abstract: A method of fabricating a tag includes the steps of applying a first patterned adhesive to the surface of the substrate and applying a first electrically conductive foil to the first patterned adhesive. A portion of the first electrically conductive foil not adhered to the first patterned adhesive is removed and a second patterned adhesive is applied to a portion of a surface area of the tag. A preformed second electrically conductive foil is applied to the second patterned adhesive to adhere the second electrically conductive foil to the surface of the substrate and portions of the first and second electrically conductive foils are electrically coupled to each other to form a tag circuit. A second patterned adhesive can be disposed between the first and second electrically conductive foils.
    Type: Application
    Filed: September 19, 2006
    Publication date: January 18, 2007
    Applicant: CHECKPOINT SYSTEMS, INC.
    Inventor: Andre Cote
  • Patent number: 7138919
    Abstract: A method for processing a surface of an item and providing an association using a surface processing system includes receiving an item having a first identification marking on a surface of the item to provide a received item for providing a first identification signal in response to a first interrogation signal and applying a second identification marking to the surface of the item for providing a second identification signal in response to a second interrogation signal. At least one of the first and second interrogation signals is applied to the item to provide at least one of the first and second identification signals. At least one of the first and second identification signals is received in response to the at least one of the first and second interrogation signals. An association is made is determined in response to the first receiving.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: November 21, 2006
    Assignee: Checkpoint Systems, Inc.
    Inventors: Thomas J. Clare, Andre Cote
  • Patent number: 7119685
    Abstract: A circuit element the presence of the circuit element includes first and second capacitor plates disposed over the surface of the substrate in an aligned relationship with each other. The aligned relationship has manufacturing variations in the relative positioning of the first and second capacitor plates and a dielectric layer disposed between the first and second capacitor plates. At least one of the first and second capacitor plates is formed substantially smaller relative to the other of the first and second capacitor plates. The at least one of the capacitor plates is disposed at a predetermined offset in at least one planar direction from an edge of the other of the first and second capacitor plates. The predetermined offset is selected according to the manufacturing variations to prevent variations in the value of capacitance of the capacitor due to the manufacturing variations.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: October 10, 2006
    Assignee: Checkpoint Systems, Inc.
    Inventors: Eric Eckstein, Andre Cote
  • Patent number: 7116227
    Abstract: A tag having a substrate having a surface with a preformed first patterned adhesive disposed over the surface thereof and a first layer of electrically conductive material having a shape corresponding to a desired final pattern for a first electrically conductive trace secured to the surface of the substrate. The preformed first patterned adhesive corresponds to the desired final pattern. A second patterned adhesive is disposed over a portion of a surface area of the tag. An electrically conductive trace is disposed over the second patterned adhesive to adhere the second electrically conductive trace thereto. An electrical connection is provided for electrically coupling portions of the first and second electrically conductive traces to form a tag circuit. The tag circuit can be an LC resonant circuit. The preformed first patterned adhesive can be a flexographic printed layer.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: October 3, 2006
    Assignee: Checkpoint Systems, Inc.
    Inventors: Eric Eckstein, Andre Cote
  • Publication number: 20060185790
    Abstract: A method of fabricating a tag includes the steps of applying a first patterned adhesive to the surface of the substrate and applying a first electrically conductive foil to the first patterned adhesive. A portion of the first electrically conductive foil not adhered to the first patterned adhesive is removed and a second patterned adhesive is applied to a portion of a surface area of the tag. A preformed second electrically conductive foil is applied to the second patterned adhesive to adhere the second electrically conductive foil to the surface of the substrate and portions of the first and second electrically conductive foils are electrically coupled to each other to form a tag circuit. A second patterned adhesive can be disposed between the first and second electrically conductive foils.
    Type: Application
    Filed: April 6, 2006
    Publication date: August 24, 2006
    Inventors: Eric Eckstein, Andre Cote
  • Publication number: 20060175003
    Abstract: A method of fabricating a tag includes the steps of applying a first patterned adhesive to the surface of the substrate and applying a first electrically conductive foil to the first patterned adhesive. A portion of the first electrically conductive foil not adhered to the first patterned adhesive is removed and a second patterned adhesive is applied to a portion of a surface area of the tag. A preformed second electrically conductive foil is applied to the second patterned adhesive to adhere the second electrically conductive foil to the surface of the substrate and portions of the first and second electrically conductive foils are electrically coupled to each other to form a tag circuit. A second patterned adhesive can be disposed between the first and second electrically conductive foils.
    Type: Application
    Filed: April 6, 2006
    Publication date: August 10, 2006
    Inventors: Eric Eckstein, Andre Cote
  • Publication number: 20060071083
    Abstract: A tag and method of making it. The tag includes a first adhesive layer provided in a first predetermined pattern between a surface of a first substrate and a first conductive foil. The first pattern corresponds to a pattern for a first conductive trace, e.g., a portion of a resonant circuit. The first conductive foil is laminated, e.g., adhesively secured, to the surface of the first substrate to form a first conductive layer. A first portion of that layer is shaped, e.g., die-cut, to generally correspond to the first pattern. A second portion of the first conductive layer not corresponding to the first portion is removed, to establish the first conductive trace, with the adhesive layer confined within the boundaries of the first conductive trace. Another conductive trace is secured to the first conductive trace, with a dielectric therebetween, to form a resonant circuit.
    Type: Application
    Filed: November 22, 2005
    Publication date: April 6, 2006
    Applicant: Checkpoint Systems, Inc.
    Inventors: Lawrence Appalucci, Andre Cote, David Perez, Gary Mazoki, Anthony Piccoli, Rolando Martinez, Luis Soler Bonnin, Takeshi Matsumoto, Hideaki Imaichi
  • Patent number: 6988666
    Abstract: A tag and method of making it. The tag includes a first adhesive layer provided in a first predetermined pattern between a surface of a first substrate and a first conductive foil. The first pattern corresponds to a pattern for a first conductive trace, e.g., a portion of a resonant circuit. The first conductive foil is laminated, e.g., adhesively secured, to the surface of the first substrate to form a first conductive layer. A first portion of that layer is shaped, e.g., die-cut, to generally correspond to the first pattern. A second portion of the first conductive layer not corresponding to the first portion is removed, to establish the first conductive trace, with the adhesive layer confined within the boundaries of the first conductive trace. Another conductive trace is secured to the first conductive trace, with a dielectric therebetween, to form a resonant circuit.
    Type: Grant
    Filed: September 5, 2002
    Date of Patent: January 24, 2006
    Assignee: Checkpoint Systems, Inc.
    Inventors: Lawrence Appalucci, Andre Cote, David Lopez Perez, Gary Thomas Mazoki, Anthony Frank Piccoli, Rolando Roques Martinez, Luis Francisco Soler Bonnin, Takeshi Matsumoto, Hideaki Imaichi
  • Publication number: 20050284917
    Abstract: A method and apparatus for bonding integrated circuits uniquely suited to high volume tag production is described, where conductive material of a substrate at the die-attach-area is cut before an IC chip or transponder is placed on the conductive material over the cut and bonded. The apparatus performs the method of placing a first chip on a substrate having a conductive layer, measuring the location of the first chip on the substrate, cutting the conductive layer at a location of an expected subsequently placed chip to form a cut based on the measured location of the first chip, and placing the subsequently placed chip on the substrate over the cut.
    Type: Application
    Filed: June 24, 2005
    Publication date: December 29, 2005
    Applicant: Checkpoint Systems, Inc.
    Inventors: Thomas Clare, Andre Cote, Eric Eckstein
  • Publication number: 20050183264
    Abstract: A circuit element the presence of the circuit element includes first and second capacitor plates disposed over the surface of the substrate in an aligned relationship with each other. The aligned relationship has manufacturing variations in the relative positioning of the first and second capacitor plates and a dielectric layer disposed between the first and second capacitor plates. At least one of the first and second capacitor plates is formed substantially smaller relative to the other of the first and second capacitor plates. The at least one of the capacitor plates is disposed at a predetermined offset in at least one planar direction from an edge of the other of the first and second capacitor plates. The predetermined offset is selected according to the manufacturing variations to prevent variations in the value of capacitance of the capacitor due to the manufacturing variations.
    Type: Application
    Filed: November 29, 2004
    Publication date: August 25, 2005
    Inventors: Eric Eckstein, Andre Cote
  • Publication number: 20050187837
    Abstract: A method for determining billing information for a tag application process for billing a customer using the tag application process, includes the steps of determining a cost component of said tag fabrication process and determining billing information in accordance with said cost component. The customer is billed in accordance with said determined billing information.
    Type: Application
    Filed: November 29, 2004
    Publication date: August 25, 2005
    Inventors: Eric Eckstein, Andre Cote
  • Publication number: 20050184872
    Abstract: A method for processing a surface of an item and providing an association using a surface processing system includes receiving an item having a first identification marking on a surface of the item to provide a received item for providing a first identification signal in response to a first interrogation signal and applying a second identification marking to the surface of the item for providing a second identification signal in response to a second interrogation signal. At least one of the first and second interrogation signals is applied to the item to provide at least one of the first and second identification signals. At least one of the first and second identification signals is received in response to the at least one of the first and second interrogation signals. An association is made is determined in response to the first receiving.
    Type: Application
    Filed: November 24, 2004
    Publication date: August 25, 2005
    Inventors: Thomas Clare, Andre Cote
  • Publication number: 20050184873
    Abstract: A tag having a substrate having a surface with a preformed first patterned adhesive disposed over the surface thereof and a first layer of electrically conductive material having a shape corresponding to a desired final pattern for a first electrically conductive trace secured to the surface of the substrate. The preformed first patterned adhesive corresponds to the desired final pattern. A second patterned adhesive is disposed over a portion of a surface area of the tag. An electrically conductive trace is disposed over the second patterned adhesive to adhere the second electrically conductive trace thereto. An electrical connection is provided for electrically coupling portions of the first and second electrically conductive traces to form a tag circuit. The tag circuit can be an LC resonant circuit. The preformed first patterned adhesive can be a flexographic printed layer.
    Type: Application
    Filed: November 24, 2004
    Publication date: August 25, 2005
    Inventors: Eric Eckstein, Andre Cote
  • Publication number: 20050183817
    Abstract: A method of fabricating a tag includes the steps of applying a first patterned adhesive to the surface of the substrate and applying a first electrically conductive foil to the first patterned adhesive. A portion of the first electrically conductive foil not adhered to the first patterned adhesive is removed and a second patterned adhesive is applied to a portion of a surface area of the tag. A preformed second electrically conductive foil is applied to the second patterned adhesive to adhere the second electrically conductive foil to the surface of the substrate and portions of the first and second electrically conductive foils are electrically coupled to each other to form a tag circuit. A second patterned adhesive can be disposed between the first and second electrically conductive foils.
    Type: Application
    Filed: November 24, 2004
    Publication date: August 25, 2005
    Inventors: Eric Eckstein, Andre Cote
  • Patent number: D523804
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: June 27, 2006
    Assignee: BRP US Inc.
    Inventors: Etienne Guay, Joseph Ellice, Steve Tetreault, Andre Cote, Eric Plumb
  • Patent number: D524224
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: July 4, 2006
    Assignee: BRP US Inc.
    Inventors: Etienne Guay, Joseph Ellice, Steve Tetreault, Andre Cote, Eric Plumb
  • Patent number: D487672
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: March 23, 2004
    Inventors: Andre Cote, Michael Boilard