Abstract: Apparatus and methods are disclosed, including maintaining a first group of tagged data from a host device at contiguous physical locations on a group of non-volatile memory cells of a storage system during system management operations on the group of non-volatile memory cells including the first group of tagged data while the first group of tagged data remains stored on the storage system and prioritizing, in the storage system, commands associated with the first group of tagged data.

Abstract: Devices and techniques to reduce corruption of received data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, in a first mode until the received data exceeds a threshold amount, and to transition from the first mode to a second mode after the received data exceeds the threshold amount.

Abstract: Devices and techniques are disclosed herein for providing an improved Replay Protected Memory Block (RPMB) data frame and command queue for communication between a host device and a memory device.

Abstract: The present invention is directed to a method for identifying a gene that regulates clostridial neurotoxin activity, the method comprising: a. providing a sample of human neuronal cells expressing a polypeptide that comprises a C-terminal detectable label, wherein the polypeptide is cleavable by a clostridial neurotoxin; b. altering expression of a target gene of the cells; c. contacting the cells with the clostridial neurotoxin; d. measuring an amount of C-terminal detectable label, thereby quantifying clostridial neurotoxin activity; and e. identifying the target gene as a regulator of clostridial neurotoxin activity when the quantified clostridial neurotoxin activity is different to the quantified clostridial neurotoxin activity when expression of the target gene is unaltered; or f.

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The configuration (e.g., the size and position) of the SLC cache may have an impact on power consumption, speed, and other performance of the memory device. An operating system of an electronic device to which the memory device is installed may wish to achieve different performance of the device based upon certain conditions detectable by the operating system. In this way, the performance of the memory device can be customized by the operating system through adjustments of the performance characteristics of the SLC cache.

Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A host logical-to-physical (L2P) table of the NAND device has an associated map. Entries in the map correspond to one or more logical addresses (LA) and indicate whether the host L2P table is current for those LAs. If the table is not current, then a request will bypass the host L2P table, using a standard device L2P lookup instead. Otherwise, the host L2P table can be used.

Abstract: Devices and techniques are disclosed herein for providing an improved Replay Protected Memory Block (RPMB) data frame and command queue for communication between a host device and a memory device.

Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A host logical-to-physical (L2P) table of the NAND device has an associated map. Entries in the map correspond to one or more logical addresses (LA) and indicate whether the host L2P table is current for those LAs. If the table is not current, then a request will bypass the host L2P table, using a standard device L2P lookup instead. Otherwise, the host L2P table can be used.

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The configuration (e.g., the size and position) of the SLC cache may have an impact on power consumption, speed, and other performance of the memory device. An operating system of an electronic device to which the memory device is installed may wish to achieve different performance of the device based upon certain conditions detectable by the operating system. In this way, the performance of the memory device can be customized by the operating system through adjustments of the performance characteristics of the SLC cache.

Abstract: Systems and methods for tracking certain activities of a plurality of animals in a feedlot involve a plurality of RF asset tags attached to the plurality of animals and a plurality of RF detector stations that are operable to read unique identifier codes associated with each of the plurality of RF asset tags. Members of the plurality of RF detector stations are positioned, at least for some, proximate to at least one water trough and at least one feed trough, and are operable to transmit data concerning the RF asset tags detected over a communication link to an asset management subsystem. Duplicate signals may be reduced, signal filtered and smoothed, and energy conserved with certain approaches taken with the RF detector stations. Other systems and devices are presented.

Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A read request is received at a controller of a NAND device. Here, the read request includes a logical address and a physical address. A a verification component that corresponds to the physical address is retrieved a NAND array of the NAND device. A verification of the read request is computed using the logical address, the physical address, and the verification component. A read operation is then modified based on the verification.

Abstract: Apparatus and methods are disclosed, including providing available data operations for the storage system processor to a host processor, identifying data operations to be performed by the storage system processor, and assigning identified data operations to the storage system processor to reduce bus traffic between the host processor and the storage system processor, to improve host processor performance, and to reduce energy use by the host processor.

Abstract: The invention relates to a device for filling a bottle with a liquid product, comprising support means for the bottle and a filling nozzle (11) arranged above the support means. The device comprises a first actuator for movement of a valve of the filling nozzle and a second actuator for movement of one of the support member and the filling nozzle between high and low positions, the actuators being connected to a control unit.

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.

Abstract: Devices and techniques to reduce corruption of received data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, in a first mode until the received data exceeds a threshold amount, and to transition from the first mode to a second mode after the received data exceeds the threshold amount.

Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

Abstract: A method is devised of deploying a network configuration in a datacenter. The network configuration includes one of more points of interconnection, a point of presence of the datacenter being one of the one or more points of interconnection. Each of the one or more points of interconnection in the network configuration is modeled through objects comprising, for each given point of interconnection, a node object representing the point of interconnection, an interface object hierarchically inferior to the node object and representing a connection to the point of interconnection, an evpnEdge object representing the transport to/from of the point of interconnection in the network, and a layer object hierarchically inferior to the evpnEdge object, and representing the characteristics of the protocol of transport to/from the point of interconnection. The network configuration is set up by a succession of commands on the objects and then pushed to the datacenter.

Abstract: Systems, methods, and computer-readable media for reducing distributed storage operation latency using segment routing. In some examples, a method can involve receiving, from a client, a message identifying an intent to store or retrieve data on a distributed storage environment, and sending to the client a segment routing (SR) list identifying storage node candidates for storing or retrieving the data. The method can involve steering a data request from the client through a path defined by the SR list based on a segment routing header (SRH) associated with the request, the SRH being configured to steer the request through the path until a storage node from the storage node candidates accepts the request. The method can further involve sending, to the client device, a response indicating that the storage node has accepted the request and storing or retrieving the data at the storage node that accepted the request.