Abstract: Apparatus and methods are disclosed, including identifying inactive data in a group of volatile memory cells of a host device, assembling identified inactive data in an offload unit of the group of volatile memory cells, and writing the offload unit of inactive data to a group of non-volatile memory cells of a storage system when the amount of inactive data in the offload unit reaches a threshold.

Abstract: An event-recording circuit for recording electrical events experienced by an internal circuit in a semiconductor device is disclosed. The event-recording circuit is coupled to the internal circuit via a spark gap circuit. The spark gap circuit includes one or more encapsulated air-gap structures that are fabricated using a process flow that matches, or is adapted from, a process flow used in fabricating the semiconductor device. The event-recording circuit further includes a recording device that has an electrical property that is changed by a signal passed by the spark gap circuit, such as an ESD or EOS signal. Accordingly, a test may be performed to determine the presence, and in some cases the extent, of the change to the electrical property in a failure analysis of the semiconductor device.

Abstract: Apparatus and methods are disclosed, including enabling communication between a memory controller and multiple memory devices of a storage system using a storage-system interface, the multiple memory devices each comprising a device controller and a group of non-volatile memory cells, and compressing data using at least one of the device controllers prior to transfer over the storage-system interface to improve an effective internal data transmission speed of the storage system.

Abstract: Systems, methods, and computer-readable media for reducing distributed storage operation latency using segment routing. In some examples, a method can involve receiving, from a client, a message identifying an intent to store or retrieve data on a distributed storage environment, and sending to the client a segment routing (SR) list identifying storage node candidates for storing or retrieving the data. The method can involve steering a data request from the client through a path defined by the SR list based on a segment routing header (SRH) associated with the request, the SRH being configured to steer the request through the path until a storage node from the storage node candidates accepts the request. The method can further involve sending, to the client device, a response indicating that the storage node has accepted the request and storing or retrieving the data at the storage node that accepted the request.

Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A read request is received at a controller of a NAND device. Here, the read request includes a logical address and a physical address. A a verification component that corresponds to the physical address is retrieved a NAND array of the NAND device. A verification of the read request is computed using the logical address, the physical address, and the verification component. A read operation is then modified based on the verification.

Abstract: Techniques are provided for storing data in a distributed storage system. A server stores an object according to a first storage policy in the distributed storage system that includes a plurality of storage nodes. Storing the object according to the first storage policy results in a first storage overhead for the object. The server receives a triggering event associated with the object, and the triggering event changes an attribute of the object. In response to the triggering event, the server identifies a second storage policy for the object. Storing the object according to the second storage policy results in a second storage overhead for the object different from the first storage overhead.

Abstract: Apparatus and methods are disclosed, including identifying and tagging data in a group of volatile memory cells of a host device to be written to and maintained contiguously on non-volatile memory of a storage system, and writing the tagged data to the group of non-volatile memory cells. A host device includes a host processor and the group of volatile memory cells, and a storage system includes the group of non-volatile memory cells.

Abstract: Devices, methods, and machine-readable mediums are disclosed to create NAND-level logical partitions instead of physical partitions, for example, in a common pool of memory of a NAND memory device. A command can be received from a host to create a physical partition in a common pool of memory of the NAND memory device. A NAND-level logical partition can be created in the common pool of memory, instead of creating the physical partition, without allocating specific memory cells of the common pool of memory to the NAND-level logical partition. A response can be sent to the host indicative that the physical partition in the common pool of memory has been created, the response comprising a partition identifier and a range of Logical Block Addresses (LBAs) for the partition in the common pool of memory.

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.

Abstract: Disclosed in some examples are methods, systems, memory devices, machine readable mediums configured to intentionally degrade NAND performance when a value of a NAND health metric indicates a potential for failure to encourage users to replace or backup their devices before data loss occurs. For example, the system may track a NAND health metric and when that metric reaches a predetermined threshold or state, the system may intentionally degrade performance. This performance degradation may be more effective than a warning to effect device backup or replacement.

Abstract: Retrieving content in an Internet Protocol version 6 (IPv6) network may be provided. A lookup request associated with content may be received from a network node at a server having a mapping database. A response having an ordered list of more than one IPv6 addresses may be generated. The ordered list of the more than on IPv6 addresses may include IPV6 prefixes. Each of the more than one IPv6 addresses may include a first portion having a content identifier and a second portion having an indication of a location of the content. The response may be transmitted to the network node.

Abstract: Devices and techniques for implementing quality-of-service (QoS) parameters in a managed memory device having a number of memory dies are disclosed herein.

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

Abstract: Various implementations disclosed herein provide a search engine that receives a search request from a sensor gateway, and provides search results in return. In various implementations, the search request includes a first set of measurements captured by a first sensor, a first measurement from the first set of measurements is outside a defined range. In various implementations, the search engine determines a first feature vector based on the first set of measurements, and identifies a second feature vector that indicates a second set of measurements within a degree of similarity to the first set of measurements. In some implementations, the second set of measurements are captured by a second sensor. In various implementations, the search engine determines a search result based on the second feature vector, and transmits the search result. In some implementations, the search result indicates one or more instructions executable by the first sensor.

Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A read request is received at a controller of a NAND device. Here, the read request includes a logical address and a physical address. A a verification component that corresponds to the physical address is retrieved a NAND array of the NAND device. A verification of the read request is computed using the logical address, the physical address, and the verification component. A read operation is then modified based on the verification.

Abstract: Apparatus and methods are disclosed, including providing available data operations for the storage system processor to a host processor, identifying data operations to be performed by the storage system processor, and assigning identified data operations to the storage system processor to reduce bus traffic between the host processor and the storage system processor, to improve host processor performance, and to reduce energy use by the host processor.

Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.

Abstract: Disclosed in some examples are methods, systems, machine-readable mediums, and NAND devices which create logical partitions when requested to create a physical partition. The controller on the NAND mimics the creation of the physical partition to the host device that requested the physical partition. Thus, the host device sees the logical partition as a physical partition. Despite this, the NAND does not incur the memory storage expense of creating a separate partition, and additionally the NAND can borrow cells for overprovisioning from another partition. In these examples, a host device operating system believes that a physical partition has been created, but the NAND manages the memory as a contiguous pool of resources. Thus, a logical partition is created at the NAND memory controller level—as opposed to at the operating system level.

Abstract: The invention relates to a filler spout comprising a tubular body having mounted therein both a valve member extending facing an inlet orifice of a distribution chamber and also a shutter arranged downstream from the valve member and rigidly connected thereto in such a manner as to extend facing an outlet orifice of the distribution chamber. An actuator is coupled to the valve member in order to move it between an extreme opening position and an extreme closing position, the valve member possessing an intermediate closing position in order to form a suction piston when the valve member is moved from the extreme closing position to the intermediate closing position or from the intermediate closing position to the extreme closing position. The shutter includes a channel opening into the distribution chamber and facing the outlet orifice of said distribution chamber so that the channel is always unobstructed regardless of the position of the valve member.