Patents by Inventor Andrea Corrion
Andrea Corrion has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128367Abstract: A HEMT comprising a channel layer of a first III-Nitride semiconductor material, grown on a N-polar surface of a back barrier layer of a second III-Nitride semiconductor material; the second III-Nitride semiconductor material having a larger band gap than the first III-Nitride semiconductor material, such that a positively charged polarization interface and two-dimensional electron gas is obtained in the channel layer; a passivation, capping layer, of said first III-Nitride semiconductor material, formed on top of and in contact with a first portion of a N-polar surface of said channel layer; a gate trench traversing the passivation, capping layer, and ending at said N-polar surface of said channel layer; and a gate conductor filling said gate trench.Type: ApplicationFiled: December 22, 2023Publication date: April 18, 2024Applicant: HRL Laboratories, LLCInventors: Daniel DENNINGHOFF, Andrea CORRION, Fevzi ARKUN, Micha FIREMAN
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Publication number: 20220069114Abstract: A HEMT comprising a channel layer of a first III-Nitride semiconductor material, grown on a N-polar surface of a back barrier layer of a second III-Nitride semiconductor material; the second III-Nitride semiconductor material having a larger band gap than the first III-Nitride semiconductor material, such that a positively charged polarization interface and two-dimensional electron gas is obtained in the channel layer; a passivation, capping layer, of said first III-Nitride semiconductor material, formed on top of and in contact with a first portion of a N-polar surface of said channel layer; a gate trench traversing the passivation, capping layer, and ending at said N-polar surface of said channel layer; and a gate conductor filling said gate trench.Type: ApplicationFiled: May 4, 2021Publication date: March 3, 2022Applicant: HRL Laboratories, LLCInventors: Daniel DENNINGHOFF, Andrea Corrion, Fevzi Arkun, Micha Fireman
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Patent number: 10714605Abstract: A transistor includes a substrate, a channel layer coupled to the substrate, a source electrode coupled to the channel layer, a drain electrode coupled to the channel layer, and a gate electrode coupled to the channel layer between the source electrode and the drain electrode. The gate electrode has a length dimension of less than 50 nanometers near the channel layer, and the channel layer includes at least a first GaN layer and a first graded AlGaN layer on the first GaN layer.Type: GrantFiled: December 12, 2018Date of Patent: July 14, 2020Assignee: HRL Laboratories, LLCInventors: Jeong-Sun Moon, Andrea Corrion, Joel C. Wong, Adam J. Williams
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Patent number: 10418473Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.Type: GrantFiled: February 7, 2018Date of Patent: September 17, 2019Assignee: HRL Laboratories, LLCInventors: David F. Brown, Keisuke Shinohara, Miroslav Micovic, Andrea Corrion
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Publication number: 20190252535Abstract: A transistor includes a substrate, a channel layer coupled to the substrate, a source electrode coupled to the channel layer, a drain electrode coupled to the channel layer, and a gate electrode coupled to the channel layer between the source electrode and the drain electrode. The gate electrode has a length dimension of less than 50 nanometers near the channel layer, and the channel layer includes at least a first GaN layer and a first graded AlGaN layer on the first GaN layer.Type: ApplicationFiled: December 12, 2018Publication date: August 15, 2019Applicant: HRL Laboratories, LLCInventors: Jeong-Sun MOON, Andrea CORRION, Joel C. WONG, Adam J. WILLIAMS
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Patent number: 10325997Abstract: A HEMT device comprising a III-Nitride material substrate, the surface of which follows a plane that is not parallel to the C-plane of the III-Nitride material; an epitaxial layer of III-Nitride material grown on said substrate; a recess etched in said epitaxial layer, having at least one plane wall parallel to a polar plane of the III-Nitride material; a carrier supply layer formed on a portion of the plane wall of the recess, such that a 2DEG region is formed along the portion of the plane wall of the recess; a doped source region formed at the surface of said epitaxial layer such that the doped source region is separated from said 2DEG region by a channel region of the epitaxial layer; a gate insulating layer formed on the channel region of the epitaxial layer; and a gate contact layer formed on the gate insulating layer.Type: GrantFiled: October 5, 2016Date of Patent: June 18, 2019Assignee: HRL Laboratories, LLCInventors: Sameh G. Khalil, Andrea Corrion, Karim S. Boutros
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Patent number: 10217648Abstract: Methods using chemical vapor deposition (CVD) of diamond deposited on a sacrificial material provide CVD diamond microchannel structures and 3-D interconnection structures of CVD diamond microfluidic channels. The sacrificial material is patterned to define locations and dimensions of the microchannels. The patterned sacrificial material is selectively removed from underneath the chemical vapor deposited (CVD) diamond to form the CVD diamond microchannels. The CVD diamond microchannels are integrated with electronic structures to provide an integral microfluidic cooling system to electronic devices.Type: GrantFiled: May 31, 2017Date of Patent: February 26, 2019Assignee: HRL Laboratories, LLCInventors: David F. Brown, Keisuke Shinohara, Miroslav Micovic, Alexandros Margomenos, Andrea Corrion, Hector L. Bracamontes, Ivan Alvarado-Rodriguez
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Patent number: 9954090Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.Type: GrantFiled: May 6, 2016Date of Patent: April 24, 2018Assignee: HRL Laboratories, LLCInventors: David F. Brown, Keisuke Shinohara, Miroslav Micovic, Andrea Corrion
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Patent number: 9929243Abstract: A method of making a stepped field gate for an FET including forming a first passivation layer on a barrier layer, defining a first field plate by using electron beam (EB) lithography and by depositing a first negative EB resist, forming a second passivation layer over first negative EB resist and the first passivation layer, planarizing the first negative EB resist and the second passivation layer, defining a second field plate by using EB lithography and by depositing a second negative EB resist connected to the first negative EB resist, forming a third passivation layer over second negative EB resist and the second passivation layer, planarizing the second negative EB resist and the third passivation layer, removing the first and second negative EB resist, and forming a stepped field gate by using lithography and plating in a void left by the removed first and second negative EB resist.Type: GrantFiled: August 3, 2015Date of Patent: March 27, 2018Assignee: HRL Laboratories, LLCInventors: Andrea Corrion, Keisuke Shinohara, Miroslav Micovic, Rongming Chu, David F. Brown, Alexandros D. Margomenos, Shawn D. Burnham
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Publication number: 20170025518Abstract: A HEMT device comprising a III-Nitride material substrate, the surface of which follows a plane that is not parallel to the C-plane of the III-Nitride material; an epitaxial layer of III-Nitride material grown on said substrate; a recess etched in said epitaxial layer, having at least one plane wall parallel to a polar plane of the III-Nitride material; a carrier supply layer formed on a portion of the plane wall of the recess, such that a 2DEG region is formed along the portion of the plane wall of the recess; a doped source region formed at the surface of said epitaxial layer such that the doped source region is separated from said 2DEG region by a channel region of the epitaxial layer; a gate insulating layer formed on the channel region of the epitaxial layer; and a gate contact layer formed on the gate insulating layer.Type: ApplicationFiled: October 5, 2016Publication date: January 26, 2017Applicant: HRL Laboratories, LLCInventors: Sameh G. KHALIL, Andrea Corrion, Karim S. Boutros
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Patent number: 9496197Abstract: Apparatus and methods are provided for heat removal and spreading from a field effect transistor (FET) including a substrate, a first source, a first gate, and a drain on the substrate, and a poly-diamond dielectric thermally coupled to the first gate wherein the poly-diamond dielectric facilitates heat removal from a top of the FET.Type: GrantFiled: September 24, 2014Date of Patent: November 15, 2016Assignee: HRL Laboratories, LLCInventors: Miroslav Micovic, Alexandros D. Margomenos, Keisuke Shinohara, Andrea Corrion
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Patent number: 9490357Abstract: A HEMT device comprising a III-Nitride material substrate, the surface of which follows a plane that is not parallel to the C-plane of the III-Nitride material; an epitaxial layer of III-Nitride material grown on said substrate; a recess etched in said epitaxial layer, having at least one plane wall parallel to a polar plane of the III-Nitride material; a carrier supply layer formed on a portion of the plane wall of the recess, such that a 2DEG region is formed along the portion of the plane wall of the recess; a doped source region formed at the surface of said epitaxial layer such that the doped source region is separated from said 2DEG region by a channel region of the epitaxial layer; a gate insulating layer formed on the channel region of the epitaxial layer; and a gate contact layer formed on the gate insulating layer.Type: GrantFiled: July 11, 2014Date of Patent: November 8, 2016Assignee: HRL Laboratories, LLCInventors: Sameh G. Khalil, Andrea Corrion, Karim S. Boutros
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Patent number: 9419122Abstract: A method of making a stepped field gate for an FET including forming a first set of layers having a passivation layer on a barrier layer of the FET and a first etch stop layer over the first passivation layer, forming additional sets of layers having alternating passivation layer and etch stop layers, successively removing portions of each set of layers using lithography and reactive ion etching to form stepped passivation layers and a gate foot, applying a mask having an opening defining an extent of a stepped field-plate gate, and forming the stepped field plate gate and the gate foot by plating through the opening in the mask.Type: GrantFiled: September 29, 2015Date of Patent: August 16, 2016Assignee: HRL Laboratories, LLCInventors: Andrea Corrion, Keisuke Shinohara, Miroslav Micovic, Rongming Chu, David F. Brown, Adam J. Williams, Dean C. Regan, Joel C. Wong
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Patent number: 9378949Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.Type: GrantFiled: June 23, 2014Date of Patent: June 28, 2016Assignee: HRL Laboratories, LLCInventors: David F. Brown, Keisuke Shinohara, Miroslav Micovic, Andrea Corrion
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Patent number: 9252247Abstract: The interface resistance between the source/drain and gate of an HFET may be significantly reduced by engineering the bandgap of the 2DEG outside a gate region such that the charge density is substantially increased. The resistance may be further reduced by using an n+GaN Cap layer over the channel layer and barrier layer such that a horizontal surface of the barrier layer beyond the gate region is covered by the n+GaN Cap layer. This technique is applicable to depletion and enhancement mode HFETs.Type: GrantFiled: January 10, 2014Date of Patent: February 2, 2016Assignee: HRL Laboratories, LLCInventors: Miroslav Micovic, Andrea Corrion, Keisuke Shinohara, Peter J Willadsen, Shawn D Burnham, Hooman Kazemi, Paul B Hashimoto
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Patent number: 9202880Abstract: A method of making a stepped field gate for an FET including forming a first set of layers having a passivation layer on a barrier layer of the FET and a first etch stop layer over the first passivation layer, forming additional sets of layers having alternating passivation layer and etch stop layers, successively removing portions of each set of layers using lithography and reactive ion etching to form stepped passivation layers and a gate foot, applying a mask having an opening defining an extent of a stepped field-plate gate, and forming the stepped field plate gate and the gate foot by plating through the opening in the mask.Type: GrantFiled: August 30, 2013Date of Patent: December 1, 2015Assignee: HRL Laboratories, LLCInventors: Andrea Corrion, Keisuke Shinohara, Miroslav Micovic, Rongming Chu, David F. Brown, Adam J. Williams, Dean C. Regan, Joel C. Wong
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Patent number: 9142626Abstract: A method of making a stepped field gate for an FET including forming a first passivation layer on a barrier layer, defining a first field plate by using electron beam (EB) lithography and by depositing a first negative EB resist, forming a second passivation layer over first negative EB resist and the first passivation layer, planarizing the first negative EB resist and the second passivation layer, defining a second field plate by using EB lithography and by depositing a second negative EB resist connected to the first negative EB resist, forming a third passivation layer over second negative EB resist and the second passivation layer, planarizing the second negative EB resist and the third passivation layer, removing the first and second negative EB resist, and forming a stepped field gate by using lithography and plating in a void left by the removed first and second negative EB resist.Type: GrantFiled: August 30, 2013Date of Patent: September 22, 2015Assignee: HRL Laboratories, LLCInventors: Andrea Corrion, Keisuke Shinohara, Miroslav Micovic, Rongming Chu, David F. Brown, Alexandros D. Margomenos, Shawn D. Burnham
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Patent number: 8980759Abstract: A method of forming a slanted field plate including forming epitaxy for a FET on a substrate, forming a wall near a drain of the FET, the wall comprising a first negative tone electron-beam resist (NTEBR), depositing a dielectric over the epitaxy and the wall, the wall causing the dielectric to have a step near the drain of the FET, depositing a second NTEBR over the dielectric, wherein surface tension causes the deposited second NTEBR to have a slanted top surface between the step and a source of the FET, etching anisotropically vertically the second NTEBR and the dielectric to remove the second NTEBR and to transfer a shape of the slanted top surface to the dielectric, and forming a gatehead comprising metal on the dielectric between the step and the source of the FET, wherein the gatehead forms a slanted field plate.Type: GrantFiled: May 22, 2014Date of Patent: March 17, 2015Assignee: HRL Laboratories, LLCInventors: Andrea Corrion, Joel C. Wong, Keisuke Shinohara, Miroslav Micovic, Ivan Milosavljevic, Dean C. Regan, Yan Tang
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Publication number: 20150014700Abstract: A HEMT device comprising a III-Nitride material substrate, the surface of which follows a plane that is not parallel to the C-plane of the III-Nitride material; an epitaxial layer of III-Nitride material grown on said substrate; a recess etched in said epitaxial layer, having at least one plane wall parallel to a polar plane of the III-Nitride material; a carrier supply layer formed on a portion of the plane wall of the recess, such that a 2DEG region is formed along the portion of the plane wall of the recess; a doped source region formed at the surface of said epitaxial layer such that the doped source region is separated from said 2DEG region by a channel region of the epitaxial layer; a gate insulating layer formed on the channel region of the epitaxial layer; and a gate contact layer formed on the gate insulating layer.Type: ApplicationFiled: July 11, 2014Publication date: January 15, 2015Inventors: Sameh G. Khalil, Andrea Corrion, Karim S. Boutros
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Patent number: 8796736Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.Type: GrantFiled: May 17, 2013Date of Patent: August 5, 2014Assignee: HRL Laboratories, LLCInventors: David F. Brown, Keisuke Shinohara, Miroslav Micovic, Andrea Corrion