SELF-PASSIVATED NITROGEN-POLAR III-NITRIDE TRANSISTOR
A HEMT comprising a channel layer of a first III-Nitride semiconductor material, grown on a N-polar surface of a back barrier layer of a second III-Nitride semiconductor material; the second III-Nitride semiconductor material having a larger band gap than the first III-Nitride semiconductor material, such that a positively charged polarization interface and two-dimensional electron gas is obtained in the channel layer; a passivation, capping layer, of said first III-Nitride semiconductor material, formed on top of and in contact with a first portion of a N-polar surface of said channel layer; a gate trench traversing the passivation, capping layer, and ending at said N-polar surface of said channel layer; and a gate conductor filling said gate trench.
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The present application claims priority to, and the benefit of, U.S. Provisional Patent Application No. 63/071,912, filed Aug. 28, 2020, and entitled “Self-Passivated Nitrogen-Polar III-Nitride Transistor.
TECHNICAL FIELDEmbodiments of the present disclosure relate to High Electron Mobility Transistors made on the N-polar surface of a III-Nitride semiconductor, as well as methods of manufacturing thereof.
BACKGROUNDIII-Nitride HEMTs, in particular GaN HEMTs, are being increasingly implemented in monolithic microwave integrated circuit (MMIC) amplifiers due to an outstanding combination of properties such as speed, output power, and efficiency for transmit applications, and linearity, noise figure, and RF input survivability for receive applications. Such HEMTs can be used in high-frequency and high-power applications such as: broadband transmitters for electronic warfare jamming, phased array radars, Ka-band missile seekers, satellite communication ground terminals, high-power devices for cellular base station applications, and high-voltage devices for switching applications. The vast majority of GaN HEMTs is reported to-date have utilized a base semiconductor crystal in the [0001], or gallium-polar (Ga-polar), crystallographic orientation. However, recent reports of [000-1]-oriented GaN HEMTs—so-called “N-polar” GaN—have shown tremendous potential for high-power, high-frequency RF performance. In particular, N-polar GaN HEMTs with recessed gates and GaN cap layers have produced record output power at millimeter-wave frequencies. See for example Wienecke, Steven, et al. “N-polar GaN cap MISHEMT with record power density exceeding 6.5 W/mm at 94 GHz.” IEEE Electron Device Letters 38.3 (2017): 359-362; and Romanczyk, Brian, et al. “Demonstration of constant 8 W/mm power density at 10, 30, and 94 GHz in state-of-the-art millimeter-wave N-polar GaN MISHEMTs.” IEEE Transactions on Electron Devices 65.1 (2017): 45-50; and also Guidry, Matthew, et al. “Demonstration of 30 GHz OIP3/PDC 10 dB by mm-Wave N-polar Deep Recess MISHEMTs”. University of California Santa Barbara United States, 2019.
High-frequency N-polar AlxGa1-xN/GaN HEMTs known from the above references have a GaN channel layer formed on the N-polar surface of an AlxGa1-xN barrier layer, and have a thick GaN cap layer above the channel layer that acts as a highly effective surface passivation layer to limit DC-to-RF dispersion and allows high output power, while a gate recess allows vertical scaling for high-frequency operation. These high frequency N-polar AlxGa1-xN/GaN HEMTs also have a secondary, thin AlGaN etch stop layer above the channel layer and under the thick GaN cap. The thin etch stop is used to form the gate foot of these HEMTs, by accurately terminating a deep dry etch of the gate recess or trench in the capping material.
However, several disadvantages to incorporating this secondary AlGaN layer include: the formation of a secondary parasitic channel at the top secondary AlGaN layer/GaN cap layer interface in the access regions (between gate and source and between gate and drain); increased oxygen incorporation, alloy scattering and additional growth interrupts inherent to an additional Al-containing layer in the device structure; and channel charge depletion due to increased band bending at the secondary AlGaN layer. Moreover, the selectivity between the etch material and etch stop is not sufficiently high in etching systems, which prevents this process from being adopted in manufacturing. Thus, the thin AlGaN etch stop layer limits the performance of the known N-Polar HEMTs and is not an effective etch stop for practical use.
SUMMARYEmbodiments of the present disclosure comprise improved high-frequency and power performance high-scaled millimeter wave (mmW) N-polar AlxGa1-xN/GaN HEMTs, as well as methods for fabricating same. Such HEMTs can be integrated in MMIC technology. Embodiments of the present disclosure avoid the problems of the above-described HEMTs by altogether removing the thin etch stop layer from the layer structure in the access regions of the HEMT, and instead complete the device with an additive regrowth to insulate the channel from surface effects while maintaining a high aspect ratio. In addition to suppressing the detrimental effects of the etch stop layer under the access regions, secondary benefits of embodiments of this presentation include the elimination of etch damage under the gate foot and provide a manufacturable method of achieving the desired structure.
Embodiments of this presentation comprise, as illustrated for example in
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Other embodiments of this presentation relate to the following concepts:
Concept 1. A method of manufacturing a HEMT, the method comprising:
-
- (as for example illustrated in
FIGS. 8A, 20A ), forming a channel layer (for example 32; 118) of a first III-Nitride semiconductor material on a N-polar surface of a back barrier layer (for example 34) of a second III-Nitride semiconductor material, said back barrier layer having been formed on a top surface of a first epitaxial structure (for example 54, 56, 58); - (as for example illustrated in
FIGS. 8B, 20B ), forming a source contact layer (for example 45) and a drain contact layer (for example 46) of a third III-Nitride semiconductor on a first portion (for example 47) of a N-polar surface (for example 40) of the channel layer (for example 32), by: - forming on said N-polar surface (for example 40) of the channel layer a contacts mask (for example 70) exposing said first portion (for example 47) of said N-polar surface (for example 40) of the channel layer, but masking a second portion (for example) 38 of said N-polar surface (for example 40) of the channel layer;
- (as for example illustrated in
FIGS. 8C, 20C ), growing said source contact layer (for example 45) and said drain contact layer (for example 46) on said first portion (for example 47) of said N-polar surface (for example) 40 of the channel layer; and - removing said contacts mask (for example 70), thus exposing said second portion (for example 38) of said N-polar surface (for example 40) of the channel layer;
- (as for example illustrated in
FIG. 8D, 20D ) forming a capping layer mask (for example 72) on top of at least a portion of said source contact layer (for example 45) and said drain contact layer (for example 46) and on top of a gate region (for example 74) of said N-polar surface (for example) 40 of the channel layer, located within said second portion (for example 38) of said N-polar surface (for example) 40 of the channel layer, thus exposing a part of said second portion (for example 38) of said N-polar surface (for example) 40 of the channel layer; - (as for example illustrated in
FIG. 8E, 20E ), growing a capping layer (for example 36) of said first III-Nitride semiconductor material on top of and in contact with the exposed part of the second portion (for example 38) of said N-polar surface (for example) 40 of the channel layer, said capping layer (for example 36) contacting at least side edges of said source contact layer (for example 45) and said drain contact layer (for example 46); and removing said capping layer mask (for example 72), thus forming a gate trench (for example 42) that traverses said capping layer (for example 36) and ends at said N-polar surface (for example 40) of the channel layer; - (as for example illustrated in
FIG. 8F, 20F ), filling said gate trench (for example 42) with a gate conductor (for example 44); and - forming a source conductor (for example 48) and a drain conductor (for example 49) respectively on top of said source contact layer (for example 45) and said drain contact layer (for example 46).
- (as for example illustrated in
Concept 2. The method of Concept 1, wherein said first epitaxial structure (54, 56, 58) comprises a buffer layer (for example 58) formed on top of a nucleation layer (for example 56) formed on top of a substrate (for example 54).
Concept 3. The method of Concept 1, wherein (as illustrated for example in
Concept 4. The method of Concept 1, wherein (as illustrated for example in
Concept 5. The method of Concept 1, wherein (as illustrated for example in
Concept 6. The method of Concept 1, wherein said first III-Nitride semiconductor material is GaN, said second III-Nitride semiconductor material is AlGaN, and said third III-Nitride semiconductor material is n+ doped GaN or n+ doped InGaN.
Concept 7. A method of manufacturing a HEMT, the method comprising:
-
- (as for example illustrated in
FIGS. 12A, 13A ), forming a channel layer (for example 32) of a first III-Nitride semiconductor material on a N-polar surface of a back barrier layer (for example 34) of a second III-Nitride semiconductor material, said back barrier layer having been formed on a top surface of a first epitaxial structure (for example 54, 56, 58); - (as for example illustrated in
FIGS. 12B, 13D ), forming a source contact layer (for example 45) and a drain contact layer (for example 46) of a third III-Nitride semiconductor on a first portion (for example 47) of a N-polar surface (for example 40) of the channel layer (for example 32), by: - forming on said N-polar surface (for example 40) of the channel layer a contacts mask (for example 70) exposing said first portion (for example 47) of said N-polar surface (for example 40) of the channel layer, but masking a second portion (for example) 38 of said N-polar surface (for example 40) of the channel layer;
- (as for example illustrated in
FIGS. 12C, 13E ), growing said source contact layer (for example 45) and said drain contact layer (for example 46) on said first portion (for example 47) of said N-polar surface (for example) 40 of the channel layer; and - removing said contacts mask (for example 70), thus exposing said second portion (for example 38) of said N-polar surface (for example 40) of the channel layer;
- (as for example illustrated in
FIG. 12D, 13F ) forming a first capping layer mask (for example 72′) on top of at least a portion of said source contact layer (for example 45) and covering completely said drain contact layer (for example 46) and a gate region of said N-polar surface (for example) 40 of the channel layer, located within said second portion (for example 38) of said N-polar surface (for example) 40 of the channel layer, thus exposing a first part of said second portion (for example 38′) of said N-polar surface (for example) 40 of the channel layer, between said gate region and said source contact layer (for example 45); - (as for example illustrated in
FIG. 12E, 13G ), growing a first portion of capping layer (for example 36′) of said first III-Nitride semiconductor material on top of and in contact with the exposed first part of the second portion (for example 38′) of said N-polar surface (for example 40) of the channel layer, said first portion of capping layer (for example 36′) contacting at least side edges of said source contact layer (for example 45); and removing said first capping layer mask (for example 72′); - (as for example illustrated in
FIG. 12F, 13H ) forming a second capping layer mask (for example 72″) on top of at least a portion of said drain contact layer (for example 46) and covering completely said source contact layer (for example 45) and said gate region of said N-polar surface (for example) 40 of the channel layer, thus exposing a second part of said second portion (for example 38″) of said N-polar surface (for example) 40 of the channel layer, between said gate region and said drain contact layer (for example 46); - (as for example illustrated in
FIG. 12G, 13I ), growing a second portion of capping layer (for example 36″) of said first III-Nitride semiconductor material on top of and in contact with the exposed second part of the second portion (for example 38″) of said N-polar surface (for example 40) of the channel layer, said second portion of capping layer (for example 36″) contacting at least side edges of said drain contact layer (for example 46); and removing said second capping layer mask (for example 72″), thus forming a gate trench (for example 42) that traverses said capping layer (for example 36′, 36″) and ends at said N-polar surface (for example 40) of the channel layer; - (as for example illustrated in
FIG. 12H, 13J ), filling said gate trench (for example 42) with a gate conductor (for example 44); and - forming a source conductor (for example 48) and a drain conductor (for example 49) respectively on top of said source contact layer (for example 45) and said drain contact layer (for example 46).
- (as for example illustrated in
Concept 8. The method of Concept 7, wherein said first epitaxial structure (54, 56, 58) comprises a buffer layer (for example 58) formed on top of a nucleation layer (for example 56) formed on top of a substrate (for example 54).
Concept 9. The method of Concept 7, wherein (as illustrated for example in
Concept 10. The method of Concept 7, wherein (as illustrated for example in
Concept 11. The method of Concept 7, further comprising (as illustrated for example in
Concept 12. The method of Concept 7, wherein said first III-Nitride semiconductor material is GaN, said second III-Nitride semiconductor material is AlGaN, and said third III-Nitride semiconductor material is n+ doped GaN or n+ doped InGaN.
Concept 13. The method of claim Concept 11, wherein said first III-Nitride semiconductor material is GaN, said second III-Nitride semiconductor material is AlGaN, said third III-Nitride semiconductor material is n+ doped GaN or n+ doped InGaN, and said fourth III-Nitride semiconductor is AlGaN.
Concept 14. The method of claim 7, wherein the channel layer (for example 32) has a first doping level and the source (for example 45) and drain (for example 46) contact layers have a second doping level larger than the first doping level, wherein: a source access region of said passivation, capping layer (for example 36′), arranged between the source contact layer (for example 45) and the gate trench (for example 42), has a third doping level whose magnitude is between those of the first and second doping levels; and a drain access region of said passivation, capping layer (for example 36″), arranged between the drain contact layer (for example 46) and the gate trench (for example 42), has the first doping level.
Concept 15. A method of manufacturing a HEMT, the method comprising:
-
- (as for example illustrated in
FIG. 16A ), forming a channel layer (for example 32) of a first III-Nitride semiconductor material on a N-polar surface of a back barrier layer (for example 34) of a second III-Nitride semiconductor material, said back barrier layer having been formed on a top surface of a first epitaxial structure (for example 54, 56, 58); - (as for example illustrated in
FIG. 16B ), forming a capping layer mask (for example 102) masking a gate region (for example 104) and a source contact region (for example 103) of a N-polar surface (for example 40) of the channel layer (for example 32), thus leaving exposed a first portion (for example 105) of said N-polar surface (for example 40) of the channel layer, between said gate region and said source contact region, and a second portion (for example 106) of said N-polar surface (for example 40) of the channel layer, on a side of said gate region opposite said source contact region; - (as for example illustrated in
FIG. 16B ), growing a capping layer (for example 36) of said first III-Nitride semiconductor material on top of and in contact with the exposed portions (for example 105, 106) of said N-polar surface (for example) 40 of the channel layer, and removing said capping layer mask (for example 72), thus forming a gate trench (for example 42) that traverses said capping layer (for example 36) and ends at said N-polar surface (for example 40) of the channel layer; - (as for example illustrated in
FIG. 16D ), forming a contacts mask (for example 70) above the gate trench and most of the capping layer (for example 36) such as to expose said source contact region (for example 103) as well as a portion of the capping layer (for example 92) distal from said gate recess; - (as for example illustrated in
FIG. 16E ), forming a source contact layer (for example 45) on said source contact region (for example 103) and forming a drain contact layer (for example 46′) on top of the exposed portion of the capping layer (for example 92), and removing the contacts mask, thus exposing the gate trench (for example 42); and - (as for example illustrated in
FIG. 16F ) forming a source conductor (for example 48) and a drain conductor (for example 49) respectively on top of said source contact layer (for example 45) and said drain contact layer (for example 46′), and filling the gate trench (for example 42) with a conductor (for example 44).
- (as for example illustrated in
Concept 16. The method of Concept 15, wherein said first epitaxial structure (54, 56, 58) comprises a buffer layer (for example 58) formed on top of a nucleation layer (for example 56) formed on top of a substrate (for example 54).
Concept 17. The method of Concept 15, wherein (as illustrated for example in
Concept 18. The method of Concept 15, wherein said first III-Nitride semiconductor material is GaN, said second III-Nitride semiconductor material is AlGaN, and said third III-Nitride semiconductor material is n+ doped GaN or n+ doped InGaN.
Concept 19. A method of manufacturing a HEMT, the method comprising:
-
- (as for example illustrated in
FIG. 17A ), forming a channel layer (for example 32) of a first III-Nitride semiconductor material on a N-polar surface of a back barrier layer (for example 34) of a second III-Nitride semiconductor material, said back barrier layer having been formed on a top surface of a first epitaxial structure (for example 54, 56, 58), and forming a gate barrier layer (for example 76) of a third III-Nitride semiconductor on top of said N-polar surface (for example 40) of the channel layer (for example 32) - (as for example illustrated in
FIG. 17B ), forming a gate mask (for example 72) exposing said gate barrier layer (for example 76) except above a gate region of said N-polar surface (for example 40) of the channel layer; - (as for example illustrated in
FIG. 17C ), removing said gate barrier layer (for example 76) from said N-polar surface (for example) 40 of the channel layer except above said gate region; - (as for example illustrated in
FIG. 17D ), forming a capping layer mask (for example 110) masking a source contact region (for example 103) of said N-polar surface (for example 40) of the channel layer, thus leaving exposed a first portion (for example 105) of said N-polar surface (for example 40) of the channel layer, between said gate region and said source contact region, and a second portion (for example 106) of said N-polar surface (for example 40) of the channel layer, on a side of said gate region opposite said source contact region; - (as for example illustrated in
FIG. 17E ), growing a capping layer (for example 36) of said first III-Nitride semiconductor material on top of and in contact with the exposed portions (for example 105, 106) of said N-polar surface (for example) 40 of the channel layer, and removing said gate mask (for example 72) and said capping layer mask (for example 110), thus forming a gate trench (for example 42) that traverses said capping layer (for example 36) and ends at said N-polar surface (for example 40) of the channel layer, wherein a portion (for example 52) of said gate barrier layer lies at the bottom of said gate trench (for example 42); - (as for example illustrated in
FIG. 17F ), forming a contacts mask (for example 70) above the gate trench and most of the capping layer (for example 36) such as to expose said source contact region (for example 103) as well as a portion of the capping layer (for example 92) distal from said gate recess; - (as for example illustrated in
FIG. 17G ), forming a source contact layer (for example 45) on said source contact region (for example 103) and forming a drain contact layer (for example 46′) on top of the exposed portion of the capping layer (for example 92), and removing the contacts mask, thus exposing the gate trench (for example 42); and - (as for example illustrated in
FIG. 17H ) forming a source conductor (for example 48) and a drain conductor (for example 49) respectively on top of said source contact layer (for example 45) and said drain contact layer (for example 46′), and filling the gate trench (for example 42) with a conductor (for example 44).
- (as for example illustrated in
Concept 20. The method of Concept 19, wherein said first epitaxial structure (54, 56, 58) comprises a buffer layer (for example 58) formed on top of a nucleation layer (for example 56) formed on top of a substrate (for example 54).
Concept 21. The method of Concept 19, wherein (as illustrated for example in
Concept 22. The method of Concept 19, wherein said first III-Nitride semiconductor material is GaN, said second III-Nitride semiconductor material is AlGaN, and said third III-Nitride semiconductor material is n+ doped GaN or n+ doped InGaN.
Concept 23. A method of manufacturing a HEMT, the method comprising:
-
- (as for example illustrated in
FIG. 9A ; 21A), forming a channel layer (for example 32; 118) of a first III-Nitride semiconductor material on a N-polar surface of a back barrier layer (for example 34) of a second III-Nitride semiconductor material, said back barrier layer having been formed on a top surface of a first epitaxial structure (for example 54, 56, 58); - (as for example illustrated in
FIG. 9B ; 21B) forming a capping layer mask (for example 72) on top of a gate region (for example 74) of said N-polar surface (for example) 40 of the channel layer, thus exposing a first portion of said N-polar surface (for example) 40 of the channel layer; - (as for example illustrated in
FIG. 9D ; 21D), growing a capping layer (for example 36) of said first III-Nitride semiconductor material on top of and in contact with the exposed first portion of said N-polar surface (for example) 40 of the channel layer; and removing said capping layer mask (for example 72), thus forming a gate trench (for example 42) that traverses said capping layer (for example 36) and ends at said N-polar surface (for example 40) of the channel layer; - (as for example illustrated in
FIG. 9E ; 21E), forming a source contact layer (for example 45) and a drain contact layer (for example 46) of a third III-Nitride semiconductor on distal parts of said first portion of said N-polar surface (for example 40) of the channel layer, by: - forming on said gate trench (for example 42) and on proximal parts of said capping layer (for example 36) a contacts mask (for example 70) exposing distal parts of said capping layer (for example 36);
- (as for example illustrated in
FIG. 9F ; 21F), etching away said distal parts of said capping layer (for example 36), thus exposing said distal parts of said first portion of said N-polar surface (for example 40) of the channel layer; - (as for example illustrated in
FIG. 9G ; 21G), growing said source contact layer (for example 45) and said drain contact layer (for example 46) on said distal parts of said first portion of said N-polar surface (for example 40) of the channel layer; and - removing said contacts mask (for example 70), thus exposing again said gate trench (for example 42);
- (as for example illustrated in
FIG. 9H ; 21H), filling said gate trench (for example 42) with a gate conductor (for example 44); and - forming a source conductor (for example 48) and a drain conductor (for example 49) respectively on top of said source contact layer (for example 45) and said drain contact layer (for example 46).
- (as for example illustrated in
Concept 24. The method of Concept 23, further comprising growing a gate barrier layer (for example 76) of a fourth III-Nitride semiconductor on top of said channel layer (for example 32) before said forming a capping layer mask (for example 72), whereby said gate barrier layer covers the bottom of said gate trench (for example 42).
Concept 25. The method of Concept 23, wherein said first epitaxial structure (54, 56, 58) comprises a buffer layer (for example 58) formed on top of a nucleation layer (for example 56) formed on top of a substrate (for example 54).
Concept 26. The method of Concept 23, wherein (as illustrated for example in
Concept 27. The method of Concept 23, further comprising (as illustrated for example in
Concept 28. The method of Concept 23, wherein (as illustrated for example in
Concept 29. The method of Concept 23, wherein said first III-Nitride semiconductor material is GaN, said second III-Nitride semiconductor material is AlGaN, and said third III-Nitride semiconductor material is n+ doped GaN or n+ doped InGaN, and said fourth III-Nitride semiconductor is AlGaN.
Concept 30. The method of Concept 27, wherein said first III-Nitride semiconductor material is GaN, said second III-Nitride semiconductor material is AlGaN, said third III-Nitride semiconductor material is n+ doped GaN or n+ doped InGaN, and said fourth III-Nitride semiconductor is AlGaN.
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description.
Various embodiments in accordance with the present disclosure will be described with reference to the drawings, in which:
The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.
DETAILED DESCRIPTION OF EMBODIMENTSIn the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the invention. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the invention is defined only by the appended claims and equivalents thereof. Like numbers in the figures refer to like components, which should be apparent from the context of use.
According to an embodiment of this presentation, HEMT 30 further comprises a capping layer 36 (“regrowth A”) of said first III-Nitride semiconductor material, formed on top of and in contact with a first portion 38 of N-polar surface 40 of channel layer 32. According to an embodiment of this presentation, HEMT 30 further comprises: a gate trench 42 traversing the capping layer 36 and ending at the N-polar surface 40 of the channel layer 32; and a gate conductor 44 filling gate trench 42. According to embodiments of this presentation, the material described as AlGaN is effectively an Al(x)Ga(1-x)N material. According to embodiments of this presentation, the regrown capping layer 36 functions to passivate surface traps, to prevent DC-to-RF dispersion, to increase 2DEG density in underlying epitaxial layers, and to prevent oxidation of underlying Al-containing layers.
According to embodiments of this presentation, an “N-polar” face or surface of a III-nitride semiconductor layer is the Nitrogen-polar face of the III-Nitride semiconductor layer. According to embodiments of this presentation, HEMT 30 further comprises a source (ohmic) contact layer 45 and a drain (ohmic) contact layer 46 of a further III-Nitride semiconductor, formed on a second portion 47 of the N-polar surface 40 of channel layer 32, beyond first portion 38, on opposite sides of gate trench 42. According to embodiments of this presentation, HEMT 30 further comprises a source conductor 48 and a drain conductor 49 in contact with respectively the source contact layer 45 and the drain contact layer 46. According to embodiments of this presentation, the further III-Nitride semiconductor material forming contact layers 45 and 46 is n+ doped GaN or n+ doped InGaN. As detailed hereafter, according to embodiments of this disclosure, the n+ doping concentration of the ohmic contact regions 45 and 46 can be comprised between 1×10{circumflex over ( )}19 and 9×10{circumflex over ( )}20 cm-3 (one times 10 to the power 19 to 9 times 10 to the power 20 per cubic cm).
According to embodiments of this presentation, the gate conductor 44 is part of a “T-shape” gate structure (or “T-gate”) as for example illustrated in
As illustrated in
According to embodiments of this presentation, the method further comprises forming source contact layer 45 and drain contact layer 46 (of the fourth III-V semiconductor) on a portion 47 of the N-polar surface 40 of the channel layer 32, by forming on said N-polar surface 40 a contacts mask 70 exposing said portion 47 of N-polar surface 40, but masking a portion 38 of N-polar surface 40 (
According to embodiments of this presentation, the method further comprises forming a capping layer mask 72 exposing portion 38 of surface 40, except a gate region 74 of surface 40, located within portion 38. According to embodiments of this presentation, mask 72 is also arranged to expose small sections of source contact layer 45 and drain contact layer 46 neighboring the portion 38 of surface 40 (
According to embodiments of this presentation, the method further comprises growing capping layer 36 on top of and in contact with portion 38 of surface 40 (as well as on top of the sections of contact layer 45 and drain contact layer 46 left exposed by mask 72; then and removing mask 72 (
The method can then comprise finalizing HEMT 30′, by filling gate trench 42 with gate conductor 44, eventually after forming a gate dielectric 60 on the bottom and edges of the gate trench (and eventually on top of capping layer 36, as illustrated); as well as by forming source conductor 48 and drain conductor 49 (
It is to be noted that the forming of the source and drain contacts 45, 46 can alternatively take place after the forming of the capping layer 36. In such an embodiment, mask 72 only covers the gate region 74 and the capping layer is also formed in areas where the source and drain contacts are to be formed. Mask 70 is then formed on top of the capping layer to etch the capping layer and free the areas where the source and drain contacts 45, 46 are then formed. According to embodiments of this presentation, etch of the capping layer can be performed using dry plasma etching. The masks are arranged such that no gap exists at the interface between capping layer 36 and source contact layer 45 or at the interface between capping layer 36 and drain contact layer 46.
According to embodiments of this presentation, channel layer 32 has a first doping level, source and drain contact layers 45, 46 have a second doping level larger than the first doping level, and capping layer 36 has the first doping level.
According to embodiments of this presentation, the method further comprises forming a capping layer mask 72 above a gate region 74 of surface 40 of channel layer 32. (
According to embodiments of this presentation, the method further comprises growing capping layer 36 everywhere on top surface 40 (except on the portion covered by mask 72); then removing mask 72 (
According to embodiments of this presentation, the method further comprises forming source contact layer 45 and drain contact layer 46 by forming a contacts mask 70 on the capping layer 36 and the gate trench 42, exposing only portions 47 of the capping layer 36 above areas of surface 40 where the source and drain contacts are to be formed (
The method can then comprise finalizing HEMT 50′, by filling gate trench 42 with gate conductor 44, eventually after forming a gate dielectric 60 on the bottom and edges of the gate trench (and eventually on top of capping layer 36, as illustrated); as well as by forming source conductor 48 and drain conductor 49 (
It is to be noted that the forming of the source and drain contacts 45, 46 can alternatively take place before the forming of the capping layer 46, similarly to what is disclosed in relation with
As outlined above, according to embodiments of this presentation, the n+ doping concentration in the ohmic contact regions 45, 46 can be between 1×10{circumflex over ( )}19 and 9×10{circumflex over ( )}20 cm{circumflex over ( )}-3. Such heavy doping of the ohmic contact regions reduces the ohmic contact resistance. According to embodiments of this presentation, the dopant can be Si. Germanium (Ge) can also be used as an n-type dopant in GaN. According to embodiments of this presentation, channel region 32 can be “unintentionally” doped (UID), effectively having a doping concentration of between 5×10{circumflex over ( )}15 and 5×10{circumflex over ( )}16 cm{circumflex over ( )}-3. The dopant can still be Si.
According to embodiments of this presentation, the portion of capping layer 36 referenced 36′ (regrowth regions marked “Regrowth A”) can have doping concentrations of between 5×10{circumflex over ( )}15 and 1×10{circumflex over ( )}19 cm{circumflex over ( )}-3. The dopant can still be Si.
According to embodiments of this presentation, the portion of capping layer referenced as 36″ (the regrowth region marked “Regrowth C”) can have a doping concentration of between 5×10{circumflex over ( )}15 and 1×10{circumflex over ( )}19 cm{circumflex over ( )}-3, while being also lower than the doping concentration in capping layer portion 36′, such that the resistance of capping layer 36/capping layer portion 36′ is smaller than the resistance of capping layer portion 36″, thus allowing to have a higher breakdown voltage in capping layer portion 36″ than in capping layer portion 36′. The dopant can still be Si.
The method can then comprise finalizing HEMT 80, by filling gate trench 42 with gate conductor 44, eventually after forming a gate dielectric 60 on the bottom and edges of the gate trench 42; as well as by forming source conductor 48 and drain conductor 49 (
It is to be noted that the forming of the source and drain contacts 45, 46, can alternatively take place after the forming of the capping layer 46, as previously described in relation with
It is to be noted that the forming of the source and drain contacts 45, 46, can alternatively take place after the forming of the capping layer 46, as previously described in relation with
The method further comprises growing simultaneously source contact layer 45 on portion 103 of surface 40 and drain contact layer 46′ on portion 92 of the top surface of capping layer 36, on portion 106 of surface 40, then removing mask 70 (
The method further comprises growing simultaneously source contact layer 45 on portion 103 of surface 40 and drain contact layer 46′ on portion 92 of the top surface of capping layer 36 on portion 106 of surface 40, then removing mask 70 (
According to embodiments of this presentation, in the above-described methods of fabrication the regions not intended to see regrowth can be masked with SiO2 and regrowth can be performed by molecular beam epitaxy, before removing the SiO2 masks. Alternate masks, growth techniques, and process flows can be used as well (for example SiN masks or metal-organic chemical vapor phase deposition growth). The devices discussed here can use SiN gate dielectric under the gate metal, and optionally over the final regrowth cap layers as additional surface passivation, but alternate surface passivation or treatments may also be used.
The foregoing Detailed Description of exemplary and preferred embodiments is presented for purposes of illustration and disclosure in accordance with the requirements of the law. It is not intended to be exhaustive nor to limit the invention to the precise form(s) described, but only to enable others skilled in the art to understand how the invention may be suited for a particular use or implementation. The possibility of modifications and variations will be apparent to practitioners skilled in the art. No limitation is intended by the description of exemplary embodiments which may have included tolerances, feature dimensions, specific operating conditions, engineering specifications, or the like, and which may vary between implementations or with changes to the state of the art, and no limitation should be implied therefrom.
Applicant has made this disclosure with respect to the current state of the art, but also contemplates advancements and that adaptations in the future may take into consideration of those advancements, namely in accordance with the then current state of the art. It is intended that the scope of the invention be defined by the Claims as written and equivalents as applicable. Reference to a claim element in the singular is not intended to mean “one and only one” unless explicitly so stated. Moreover, no element, component, nor method or process step in this disclosure is intended to be dedicated to the public regardless of whether the element, component, or step is explicitly recited in the Claims. No claim element herein is to be construed under the provisions of 35 U.S.C. Sec. 112, sixth paragraph, unless the element is expressly recited using the phrase “means for . . . .” and no method or process step herein is to be construed under those provisions unless the step, or steps, are expressly recited using the phrase “comprising the step(s) of . . . .”
Claims
1. A HEMT comprising a channel layer of a first III-Nitride semiconductor material, grown on a N-polar surface of a back barrier layer of a second III-Nitride semiconductor material; the second III-Nitride semiconductor material having a larger band gap than the first III-Nitride semiconductor material, such that a positively charged polarization interface and two-dimensional electron gas is obtained in the channel layer; a passivation, capping layer, of said first III-Nitride semiconductor material, formed on top of and in contact with a first portion of a N-polar surface of said channel layer; a gate trench traversing the passivation, capping layer, and ending at said N-polar surface of said channel layer; and a gate conductor filling said gate trench.
2. The HEMT of claim 1, comprising a thin layer of a third III-Nitride semiconductor material in said gate trench between said gate conductor and said N-polar surface of said channel layer.
3. The HEMT of claim 1, wherein said passivation, capping layer, is a layer grown on said first portion of said N-polar surface of said channel layer.
4. The HEMT of claim 1, wherein said first III-Nitride semiconductor material is GaN and said second III-Nitride semiconductor material is AlGaN.
5. The HEMT of claim 2, wherein said third III-Nitride semiconductor material is one of AlN, InAlN, AlGaN and InAlGaN.
6. The HEMT of claim 1, comprising a source contact layer and a drain contact layer of a fourth Ill-Nitride semiconductor, formed on a second portion of said N-polar surface of said channel layer on opposite sides of said gate trench.
7. The HEMT of claim 6, wherein said channel layer has a first doping level and said source and drain contact layers have a second doping level larger than the first doping level, wherein: a source access region of said passivation, capping layer, arranged between the source contact layer and the gate trench, has a third doping level comprised between the first and second doping levels; and a drain access region of said passivation, capping layer, arranged between the drain contact layer and the gate trench, has the first doping level.
8. The HEMT of claim 6, wherein said source contact layer and said drain contact layer are layers grown on said second portion of said N-polar surface of said channel layer.
9. The HEMT of claim 6, comprising a source conductor and a drain conductor in contact with respectively said source contact layer and said drain contact layer.
10. The HEMT of claim 6, wherein said fourth II-Nitride semiconductor material is n+ doped GaN or n+ doped InGaN.
11. The HEMT of claim 1, comprising: a source contact layer of a fourth III-Nitride semiconductor, formed on a second portion of said N-polar surface of said channel layer on a first side of said gate trench; and a drain contact layer of said fourth III-Nitride semiconductor, formed on a portion of a top surface of said passivation, capping layer, on a second side of said gate trench opposite said first side of said gate trench.
12. The HEMT of claim 11, wherein said channel layer has a first doping level and said source and drain contact layers have a second doping level larger than the first doping level, wherein: a source access region of said passivation, capping layer, arranged between the source contact layer and the gate trench, has a third doping level comprised between the first and second doping levels; and a drain access region of said passivation, capping layer, arranged between under the drain contact layer and the gate trench, has the first doping level.
13. The HEMT of claim 11, wherein said source contact layer and said drain contact layer are layers grown respectively on said second portion of said N-polar surface of said channel layer and on said portion of a top surface of said capping layer.
14. The HEMT of claim 11, comprising a source conductor and a drain conductor in contact with respectively said source contact layer and said drain contact layer.
15. The HEMT of claim 6, wherein said fourth III-Nitride semiconductor material is n+ doped GaN or n+ doped InGaN.
16. The HEMT of claim 1, wherein a gate insulator layer lines the side and bottom of said gate conductor in said trench.
Type: Application
Filed: May 4, 2021
Publication Date: Mar 3, 2022
Applicant: HRL Laboratories, LLC (Malibu, CA)
Inventors: Daniel DENNINGHOFF (Malibu, CA), Andrea Corrion (Malibu, CA), Fevzi Arkun (Malibu, CA), Micha Fireman (Malibu, CA)
Application Number: 17/307,888