Abstract: A non volatile memory device architecture, suitable for speeding up and synchronize the programming steps of the cells in particular of the Flash-Nor type, of the type comprising a matrix of memory cells organized into rows and columns, at least one group of these columns being selected by at least one first enable signal by a second enable signal generated by a first decoder; the group of columns being associated with at least one Program Load PL controlled by a logic circuit comprising a first centralized portion and plural second portions associated with a respective program load sequentially updated and driven in a synchronous way to the first centralized portion.

Abstract: A device with non volatile memory cells, with optimized programming, of the type comprising a sector of matrix memory cells organized in rows and columns, with the columns organized in a plurality of global bit-lines associated with at least one plurality of local bit-lines and respectively enabled by a first select signal and by at least one second select signal generated by a decoder, these columns being associated with at least one program load PL controlled by a logic circuit and suitable for applying a programming pulse to a plurality of cells belonging to the enabled bit-lines, comprising a plurality of discharge transistors, each associated with a corresponding column controlled by a control signal complementary to the control signal of the adjacent discharge transistor.

Abstract: A method is for reducing possible errors in execution of simultaneous read and verify operations of data being modified in first and second different partitions of a memory device caused by turning on or off of a first partition's bank of sense amplifiers while a critical discrimination phase is being carried out by the second partition's bank of sense amplifiers. The method may include establishing an augmented duration of one of the read and verify operations exceeding a duration of the first partition's critical discrimination phase. The method may conditionally delay generation of a turn on or turn off signal of the first partition by a time determined by a command of termination, or by a beginning of the critical discrimination phase of the second partition when the other of the read and verify operations is in progress.

Abstract: A device with non volatile memory cells, with optimized programming, of the type comprising a sector of matrix memory cells organized in rows and columns, with the columns organized in a plurality of global bit-lines associated with at least one plurality of local bit-lines and respectively enabled by a first select signal and by at least one second select signal generated by a decoder, these columns being associated with at least one Program Load PL controlled by a logic circuit and suitable for applying a programming pulse to a plurality of cells belonging to the enabled bit lines, comprising a plurality of discharge transistors, each associated with a corresponding column controlled by a control signal complementary to the control signal of the adjacent discharge transistor.

Abstract: A device with non volatile memory cells, with optimized programming, of the type comprising a sector of matrix memory cells organized in rows and columns, with the columns organized in a plurality of global bit-lines associated with at least one plurality of local bit-lines and respectively enabled by a first select signal and by at least one second select signal generated by a decoder, these columns being associated with at least one Program Load PL controlled by a logic circuit and suitable for applying a programming pulse to a plurality of cells belonging to the enabled bit lines, comprising a plurality of discharge transistors, each associated with a corresponding column controlled by a control signal complementary to the control signal of the adjacent discharge transistor.

Abstract: A method for accessing a non volatile memory device including at least one group or sector of memory cells divided into regions programmable with two different data storage densities and accessible with at least two reading modes, for example a two-level mode and a multilevel mode. The memory regions are being organized into pages including a sub-group of memory cells for storing error correction codes of the data stored in the multilevel mode. The method includes providing at the beginning of each page at least one first cell wherein the information concerning the ECC protection or not of the whole page is to be stored. In the sub-group of cells at least one second cell intended for the storage of information concerning the programmed or erased state of the same page is provided. The content of the first and of the second cell is read before accessing, in programming, the corresponding page of the memory region.

Abstract: A non volatile memory device architecture, suitable for speeding up and synchronize the programming steps of the cells in particular of the Flash-Nor type, of the type comprising a matrix of memory cells organized into rows and columns, at least one group of these columns being selected by at least one first enable signal by a second enable signal generated by a first decoder; the group of columns being associated with at least one Program Load PL controlled by a logic circuit comprising a first centralized portion and plural second portions associated with a respective program load sequentially updated and driven in a synchronous way to the first centralized portion.

Abstract: Embodiment of a method for programming a memory device of the type comprising a matrix of memory cells divided in buffers of cells capacitively uncoupled from each other, the method comprising: first programming of said cells belonging to a buffer; second programming of said cells belonging to said buffer; said step of first programming occurs with a ramp gate voltage having first pitch and programs said cells of said buffer with higher threshold distribution and said step of second programming occurs with a ramp gate voltage having pitch lower than the pitch.

Abstract: A method prevents errors in execution of simultaneous read and verify operations on data being modified in two different partitions of a nonvolatile memory device. The errors are due to disturbances caused by turning on or by turning off a bank of sense amplifiers of a partition while a critical discrimination phase is being carried out by the bank of sense amplifiers of the other partition. The method includes establishing an increase in duration of one of the two operations for exceeding a minimum duration of a critical discrimination phase for the banks of sense amplifiers, and conditionally delaying conditioning of generation of a turn on or turn off signal of the bank of sense amplifiers for the partition in which the operation of an increase in duration is in progress by a predetermined time. The predetermined time is based on a command of termination, or a beginning of the critical discrimination phase by the bank of sense amplifiers of the other partition wherein the other operation is in progress.

Abstract: A semiconductor memory device includes a plurality of memory cells arranged according to a plurality of rows and a plurality of columns. The memory devices further includes a plurality of bit lines, each bit line being associated with a respective column of the plurality, and a selecting structure of the bit lines, to select at least one among the bit lines, keeping the remaining bit lines unselected. The memory device further includes a voltage clamping circuit structured to cause the clamping at a prescribed voltage of the unselected bit lines adjacent to a selected bit line during an access operation to the memory.

Abstract: A redundancy scheme for a memory integrated circuit having at least two memory sectors and, associated with each memory sector, a respective memory location selector for selecting memory locations within the memory sector according to an address. The redundancy scheme comprises at least one redundant memory sector adapted to functionally replace one of the at least two memory sectors, and a redundancy control circuitry for causing the functional replacement of a memory sector declared to be unusable by one of the at least one redundant memory sector; the redundancy control circuitry detects an access request to a memory location within the unusable memory sector and diverts the access request to a corresponding redundant memory location in the redundant memory sector. Associated with each memory location selector, respective power supply control means are provided adapted to selectively connect/disconnect the associated memory location selector to/from a power supply distribution line.

Abstract: A semiconductor memory device includes a plurality of memory cells arranged according to a plurality of rows and a plurality of columns. The memory devices further includes a plurality of bit lines, each bit line being associated with a respective column of the plurality, and a selecting structure of the bit lines, to select at least one among the bit lines, keeping the remaining bit lines unselected. The memory device further includes a voltage clamping circuit structured to cause the clamping at a prescribed voltage of the unselected bit lines adjacent to a selected bit line during an access operation to the memory.

Abstract: A redundancy scheme for a memory integrated circuit having at least two memory sectors and, associated with each memory sector, a respective memory location selector for selecting memory locations within the memory sector according to an address. The redundancy scheme comprises at least one redundant memory sector adapted to functionally replace one of the at least two memory sectors, and a redundancy control circuitry for causing the functional replacement of a memory sector declared to be unusable by one of the at least one redundant memory sector; the redundancy control circuitry detects an access request to a memory location within the unusable memory sector and diverts the access request to a corresponding redundant memory location in the redundant memory sector. Associated with each memory location selector, respective power supply control means are provided adapted to selectively connect/disconnect the associated memory location selector to/from a power supply distribution line.