Abstract: A Zinc Oxide (ZnO) layer deposited using Atomic Layer Deposition (ALD) over a phase-change material forms a self-selected storage device. The diode formed at the ZnO/GST interface shows both rectification and storage capabilities within the PCM architecture.

Abstract: Some embodiments include a memory array having a first memory cell adjacent to a second memory cell along a lateral direction. The second memory cell is vertically offset relative to the first memory cell. Some embodiments include a memory array having a series of data/sense lines extending along a first direction, a series of access lines extending along a second direction, and memory cells vertically between the access lines and data/sense lines. The memory cells are arranged in a grid having columns along the first direction and rows along the second direction. Memory cells in a common column and/or row as one another are arranged in two alternating sets, with a first set having memory cells at a first height and a second set having memory cells at a second height vertically offset relative to the first height. Some embodiments include methods of forming memory arrays.

Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

Abstract: Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.

Abstract: Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material structures are directly against both the electrically conductive material and the dielectric material along sidewall surfaces of the stacks. Electrode material electrically coupled with the electrically conductive material of the stacks. Some embodiments include methods of forming memory cells in which a programmable material plate is formed along a sidewall surface of a stack containing electrically conductive material and dielectric material.

Abstract: Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive structure may be a titanium-containing structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Some embodiments include a method of forming and using a fuse. The fuse is formed to have a tungsten-containing structure directly contacting an electrically conductive structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Current exceeding the predetermined level is passed through the interface to rupture the interface.

Abstract: Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material. Some embodiments include a method of forming a memory cell. Chalcogenide material may be formed over heater material. Electrically conductive material may be formed over the chalcogenide material. A thermal sink may be formed between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material.

Abstract: Some embodiments include semiconductor constructions having an electrically conductive interconnect with an upper surface, and having an electrically conductive structure over the interconnect. The structure includes a horizontal first portion along the upper surface and a non-horizontal second portion joined to the first portion at a corner. The second portion has an upper edge. The upper edge is offset relative to the upper surface of the interconnect so that the upper edge is not directly over said upper surface. Some embodiments include memory arrays.

Abstract: Some embodiments include a memory array having a first memory cell adjacent to a second memory cell along a lateral direction. The second memory cell is vertically offset relative to the first memory cell. Some embodiments include a memory array having a series of data/sense lines extending along a first direction, a series of access lines extending along a second direction, and memory cells vertically between the access lines and data/sense lines. The memory cells are arranged in a grid having columns along the first direction and rows along the second direction. Memory cells in a common column and/or row as one another are arranged in two alternating sets, with a first set having memory cells at a first height and a second set having memory cells at a second height vertically offset relative to the first height. Some embodiments include methods of forming memory arrays.

Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.

Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.

Abstract: Subject matter disclosed herein relates to techniques involving a structural relaxation (SR) phenomenon for increasing resistance of a Reset state of phase change memory.

Abstract: Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive structure may be a titanium-containing structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Some embodiments include a method of forming and using a fuse. The fuse is formed to have a tungsten-containing structure directly contacting an electrically conductive structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Current exceeding the predetermined level is passed through the interface to rupture the interface.

Abstract: Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.

Abstract: Some embodiments include semiconductor constructions having an electrically conductive interconnect with an upper surface, and having an electrically conductive structure over the interconnect. The structure includes a horizontal first portion along the upper surface and a non-horizontal second portion joined to the first portion at a corner. The second portion has an upper edge. The upper edge is offset relative to the upper surface of the interconnect so that the upper edge is not directly over said upper surface. Some embodiments include memory arrays.

Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.

Abstract: Some embodiments include memory arrays having a plurality of memory cells vertically between bitlines and wordlines. The memory cells contain phase change material. Heat shields are laterally between immediately adjacent memory cells along a bitline direction. The heat shields contain electrically conductive material and are electrically connected with the bitlines. Some embodiments include memory arrays having a plurality of memory cells arranged in a first grid. The first grid has columns along a first direction and has rows along a second direction substantially orthogonal to the first direction. First heat shields are between adjacent memory cells along the first direction and are arranged in a second grid offset from the first grid along the first direction. Second heat shields are between adjacent memory cells along the second direction, and are arranged lines in lines extending along the first direction. Some embodiments include methods for forming memory arrays.

Abstract: Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.

Abstract: Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. Some embodiments include a construction having a first series and a third series of access/sense lines extending along a first direction, and a second series of access/sense lines between the first and third series and extending along a second direction which crosses the first direction. First memory cells are between the first and second series of access/sense lines and arranged in a first memory array deck. Second memory cells are between the second and third series of access/sense lines and arranged in a second memory array deck.

Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.