Patents by Inventor Andrea Redaelli

Andrea Redaelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Techniques to access a self-selecting memory device
    Patent number: 10381075
    Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Totorelli, Andrea Redaelli, Agostino Pirovano, Fabio Pellizzer, Mario Allegra, Paolo Fantini
  • Memory including a selector switch on a variable resistance memory cell
    Patent number: 10374007
    Abstract: Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Agostino Pirovano
  • Fuses, and Methods of Forming and Using Fuses
    Publication number: 20190237284
    Abstract: Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive structure may be a titanium-containing structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Some embodiments include a method of forming and using a fuse. The fuse is formed to have a tungsten-containing structure directly contacting an electrically conductive structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Current exceeding the predetermined level is passed through the interface to rupture the interface.
    Type: Application
    Filed: April 4, 2019
    Publication date: August 1, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Giorgio Servalli
  • DRIFT MITIGATION WITH EMBEDDED REFRESH
    Publication number: 20190206506
    Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.
    Type: Application
    Filed: February 25, 2019
    Publication date: July 4, 2019
    Inventors: Innocenzo Tortorelli, Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Hongmei Wang
  • TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE
    Publication number: 20190189206
    Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 20, 2019
    Inventors: Innocenzo Tortorelli, Andrea Redaelli, Agostino Pirovano, Fabio Pellizzer, Mario Allegra, Paolo Fantini
  • MULTI-LEVEL SELF-SELECTING MEMORY DEVICE
    Publication number: 20190189203
    Abstract: Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 20, 2019
    Inventors: Andrea Redaelli, Innocenzo Tortorelli, Agostino Pirovano, Fabio Pellizzer
  • Thermally optimized phase change memory cells and methods of fabricating the same
    Patent number: 10305036
    Abstract: A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode includes a thermally insulating region having a first thermal resistivity over the first electrode and a metallic contact region interposed between the phase change material element and the thermally insulating region, where the metallic contact layer has a second thermal resistivity lower than the first thermal resistivity.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Mattia Boniardi, Andrea Redaelli
  • MIXED CROSS POINT MEMORY
    Publication number: 20190156884
    Abstract: Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 23, 2019
    Inventors: Andrea Redaelli, Innocenzo Tortorelli, Agostino Pirovano, Fabio Pellizzer
  • MIXED CROSS POINT MEMORY
    Publication number: 20190156885
    Abstract: Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 23, 2019
    Inventors: Andrea Redaelli, Innocenzo Tortorelli, Agostino Pirovano, Fabio Pellizzer
  • Methods of forming and using fuses
    Patent number: 10290456
    Abstract: Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive structure may be a titanium-containing structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Some embodiments include a method of forming and using a fuse. The fuse is formed to have a tungsten-containing structure directly contacting an electrically conductive structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Current exceeding the predetermined level is passed through the interface to rupture the interface.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: May 14, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Giorgio Servalli
  • METHODS, APPARATUSES, AND CIRCUITS FOR PROGRAMMING A MEMORY DEVICE
    Publication number: 20190140174
    Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 9, 2019
    Inventors: Andrea Redaelli, Agostino Pirovano, Umberto M. Meotto
  • MEMORY CELLS HAVING RESISTORS AND FORMATION OF THE SAME
    Publication number: 20190123105
    Abstract: The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.
    Type: Application
    Filed: December 11, 2018
    Publication date: April 25, 2019
    Inventors: Fabio Pellizzer, Andrea Redaelli, Agostino Pirovano, Innocenzo Tortorelli
  • Drift mitigation with embedded refresh
    Patent number: 10269442
    Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: April 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Hongmei Wang
  • Memory cells having resistors and formation of the same
    Patent number: 10263039
    Abstract: The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: April 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Andrea Redaelli, Agostino Pirovano, Innocenzo Tortorelli
  • METHODS OF OPERATING MEMORY DEVICES AND ELECTRONIC SYSTEMS
    Publication number: 20190081104
    Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.
    Type: Application
    Filed: November 9, 2018
    Publication date: March 14, 2019
    Inventors: Ugo Russo, Andrea Redaelli, Giorgio Servalli
  • THREE DIMENSIONAL MEMORY ARRAYS
    Publication number: 20190067371
    Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.
    Type: Application
    Filed: August 29, 2017
    Publication date: February 28, 2019
    Inventors: Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Innocenzo Tortorelli
  • MEMORY CELLS HAVING A PLURALITY OF RESISTANCE VARIABLE MATERIALS
    Publication number: 20190051350
    Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.
    Type: Application
    Filed: October 12, 2018
    Publication date: February 14, 2019
    Inventors: Ugo Russo, Andrea Redaelli, Fabio Pellizzer
  • PHASE CHANGE MEMORY STRUCTURES AND DEVICES
    Publication number: 20190044060
    Abstract: A phase change memory (PCM) cell can include a PCM layer. A first electrode and a second electrode disposed on opposite sides of the PCM layer. The first electrode, the second electrode, or both includes a metal ceramic composite material layer disposed between an upper barrier layer and a lower barrier layer and wherein the metal ceramic composite material layer provides a corresponding electrode with an electrical resistivity of from 10 mOhm-cm to 1000 mOhm-cm.
    Type: Application
    Filed: June 4, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Stephen W. Russell, Andrea Gotti, Andrea Redaelli, Enrico Varesi, Innocenzo Tortorelli, Lorenzo Fratin, Alessandro Sebastiani
  • METAL-NITRIDE-FREE VIA IN STACKED MEMORY
    Publication number: 20190043807
    Abstract: A nonvolatile memory device includes a metal silicon nitride layer on a three-dimensional (3D) crosspoint architecture, where the metal silicon nitride layer is in the memory array processing. The metal silicon nitride layer is patterned in accordance with the memory array structure, rather than being an underlying layer for a metal layer. The metal layer provides bitline or wordline select paths, and can connect to a via in parallel with the memory array stack. The metal silicon nitride layer is between the metal layer and the memory array, and is not present over the via.
    Type: Application
    Filed: June 30, 2018
    Publication date: February 7, 2019
    Inventors: Andrea REDAELLI, D. Ross ECONOMY, Mihir BOHRA
  • MEMORY STRUCTURES HAVING REDUCED VIA RESISTANCE
    Publication number: 20190043924
    Abstract: A memory structure can include a memory cell, a via, a dielectric material separating the memory cell from the via, a metal ceramic composite material layer on the memory cell and the dielectric material, and a conductive layer on the metal ceramic composite material layer and the via. The conductive layer can be in direct contact with the top surface of the via.
    Type: Application
    Filed: September 28, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Anna Maria Conti, Andrea Redaelli