Abstract: Various embodiments of a power source and method of forming such power source are disclosed. The power source can include a substrate and a cavity disposed in a first major surface of the substrate. The power source can also include radioactive material disposed within the cavity, where the radioactive material emits radiation particles; and particle converting material disposed within the cavity, where the particle converting material converts one or more radiation particles emitted by the radioactive material into light. The power source further includes a sealing layer disposed such that the particle converting material and the radioactive material are hermetically sealed within the cavity, and a photovoltaic device disposed adjacent the substrate. The photovoltaic device can convert at least a portion of the light emitted by the particle converting material that is incident upon an input surface of the photovoltaic device into electrical energy.

Abstract: Various embodiments of a power source and method of forming such power source are disclosed. The power source can include a substrate and a cavity disposed in a first major surface of the substrate. The power source can also include radioactive material disposed within the cavity, where the radioactive material emits radiation particles; and particle converting material disposed within the cavity, where the particle converting material converts one or more radiation particles emitted by the radioactive material into light. The power source further includes a sealing layer disposed such that the particle converting material and the radioactive material are hermetically sealed within the cavity, and a photovoltaic device disposed adjacent the substrate. The photovoltaic device can convert at least a portion of the light emitted by the particle converting material that is incident upon an input surface of the photovoltaic device into electrical energy.

Abstract: Various embodiments of a power source and method of forming such power source are disclosed. The power source can include a substrate and a cavity disposed in a first major surface of the substrate. The power source can also include radioactive material disposed within the cavity, where the radioactive material emits radiation particles; and particle converting material disposed within the cavity, where the particle converting material converts one or more radiation particles emitted by the radioactive material into light. The power source further includes a sealing layer disposed such that the particle converting material and the radioactive material are hermetically sealed within the cavity, and a photovoltaic device disposed adjacent the substrate. The photovoltaic device can convert at least a portion of the light emitted by the particle converting material that is incident upon an input surface of the photovoltaic device into electrical energy.

Abstract: Various embodiments of a power source and method of forming such power source are disclosed. The power source can include a substrate and a cavity disposed in a first major surface of the substrate. The power source can also include radioactive material disposed within the cavity, where the radioactive material emits radiation particles; and particle converting material disposed within the cavity, where the particle converting material converts one or more radiation particles emitted by the radioactive material into light. The power source further includes a sealing layer disposed such that the particle converting material and the radioactive material are hermetically sealed within the cavity, and a photovoltaic device disposed adjacent the substrate. The photovoltaic device can convert at least a portion of the light emitted by the particle converting material that is incident upon an input surface of the photovoltaic device into electrical energy.

Abstract: A hybrid integrated circuit in a wafer level package for an implantable medical device includes one or more passive component windings formed, at least in part, along one or more routing layers of the package. The windings may be primary and secondary windings of a transformer, wherein all or part of a magnetic core thereof is embedded in a component layer of the wafer level package. If the core includes a part bonded to a surface of the package, that part of the core may be E-shaped with legs extending into the routing layers, and, in some cases, through the routing layers. Routing layers may be formed on both sides of the component layer to accommodate the transformer windings, in some instances.

Abstract: Arrays of planar solid state batteries are stacked in an aligned arrangement for subsequent separation into individual battery stacks. Prior to stacking, a redistribution layer (RDL) is formed over a surface of each wafer that contains an array; each RDL includes first and second groups of conductive traces, each of the first extending laterally from a corresponding positive battery contact, and each of the second extending laterally from a corresponding negative battery contact. Conductive vias, formed before or after stacking, ultimately couple together corresponding contacts of aligned batteries. If before, each via extends through a corresponding battery contact of each wafer and is coupled to a corresponding conductive layer that is included in another RDL formed over an opposite surface of each wafer. If after, each via extends through corresponding aligned conductive traces and, upon separation of individual battery stacks, becomes an exposed conductive channel of a corresponding battery stack.

Abstract: A hybrid integrated circuit in a wafer level package for an implantable medical device includes one or more passive component windings formed, at least in part, along one or more routing layers of the package. The windings may be primary and secondary windings of a transformer, wherein all or part of a magnetic core thereof is embedded in a component layer of the wafer level package. If the core includes a part bonded to a surface of the package, that part of the core may be E-shaped with legs extending into the routing layers, and, in some cases, through the routing layers. Routing layers may be formed on both sides of the component layer to accommodate the transformer windings, in some instances.

Abstract: A hybrid integrated circuit in a wafer level package for an implantable medical device includes one or more passive component windings formed, at least in part, along one or more routing layers of the package. The windings may be primary and secondary windings of a transformer, wherein all or part of a magnetic core thereof is embedded in a component layer of the wafer level package. If the core includes a part bonded to a surface of the package, that part of the core may be E-shaped with legs extending into the routing layers, and, in some cases, through the routing layers. Routing layers may be formed on both sides of the component layer to accommodate the transformer windings, in some instances.

Abstract: A hybrid integrated circuit in a wafer level package for an implantable medical device includes one or more passive component windings formed, at least in part, along one or more routing layers of the package. The windings may be primary and secondary windings of a transformer, wherein all or part of a magnetic core thereof is embedded in a component layer of the wafer level package. If the core includes a part bonded to a surface of the package, that part of the core may be E-shaped with legs extending into the routing layers, and, in some cases, through the routing layers. Routing layers may be formed on both sides of the component layer to accommodate the transformer windings, in some instances.

Abstract: Arrays of planar solid state batteries are stacked in an aligned arrangement for subsequent separation into individual battery stacks. Prior to stacking, a redistribution layer (RDL) is formed over a surface of each wafer that contains an array; each RDL includes first and second groups of conductive traces, each of the first extending laterally from a corresponding positive battery contact, and each of the second extending laterally from a corresponding negative battery contact. Conductive vias, formed before or after stacking, ultimately couple together corresponding contacts of aligned batteries. If before, each via extends through a corresponding battery contact of each wafer and is coupled to a corresponding conductive layer that is included in another RDL formed over an opposite surface of each wafer. If after, each via extends through corresponding aligned conductive traces and, upon separation of individual battery stacks, becomes an exposed conductive channel of a corresponding battery stack.

Abstract: An overvoltage protection device is formed in a semiconductor substrate having a plurality of doped regions for forming semiconductor devices. The overvoltage protection device is adapted to draw current away from a device to be protected from excess voltage and has a switchable device having a terminal adapted to be coupled to a potential source of excess voltage and to the semiconductor substrate for drawing current away from the potential source of excess voltage when the switchable device is triggered, and for directing the current to the semiconductor substrate. A Zener diode is coupled to a second terminal of the switchable device to trigger the switchable device to a conducting state. The Zener diode is formed in the same doped region of the substrate as the trigger of the switchable device.

Abstract: Method and apparatus are provided for fabricating a planar transformer assembly for use in an implantable medical device. The planar transformer assembly includes a board, a first core, and a second core. The board has a first side, a second side, and an embedded winding, wherein the embedded winding includes a primary winding and a secondary winding and is at least partially embedded in the board between the first and second sides.

Abstract: Methods and apparatus are provided for an accelerometer. The apparatus includes first, second, and third substrates. The first substrate includes the first plate of a first capacitor. The second substrate includes a moveable mass that is coupled to the second substrate by at least one spring. The moveable mass is the second plate of the first capacitor and the first plate of a second capacitor. The third substrate includes the second plate of the second capacitor. The moveable mass is prevented from moving in any direction where the at least one spring is inelastically flexed. The first substrate couples to the second substrate. The third substrate couples to the second substrate. The method includes forming a moveable mass in a substrate. The moveable mass is formed having a plurality of springs coupling the moveable mass to the substrate. The moveable mass is released using a dry etch.

Abstract: A flip-chip package comprises a substrate having at least one layer and a component flip-chip mounted to the substrate, the component having a field termination ring. The flip-chip package further comprises a shield plane interposed between the at least one layer of substrate and the field termination ring.

Abstract: In one embodiment, a testing regimen is implemented to reduce test time. Specifically, a structure and method to power up and stabilize all die on the wafer prior to testing each die is implemented. More specifically, parallel powering schemes including die stabilization procedures are used to ready the wafer for testing. A wafer probe tester is indexed from one die to the next for an uninterrupted testing of all die in the wafer subsequent to all die power up and stabilization.

Abstract: A flip-chip package comprises a substrate having at least one layer and a component flip-chip mounted to the substrate, the component having a field termination ring. The flip-chip package further comprises a shield plane interposed between the at least one layer of substrate and the field termination ring.

Abstract: An overvoltage protection device is formed in a semiconductor substrate having a plurality of doped regions for forming semiconductor devices. The overvoltage protection device is adapted to draw current away from a device to be protected from excess voltage and has a switchable device having a terminal adapted to be coupled to a potential source of excess voltage and to the semiconductor substrate for drawing current away from the potential source of excess voltage when the switchable device is triggered, and for directing the current to the semiconductor substrate.

Abstract: In one embodiment, a testing regimen is implemented to reduce test time. Specifically, a structure and method to power up and stabilize all die on the wafer prior to testing each die is implemented. More specifically, parallel powering schemes including die stabilization procedures are used to ready the wafer for testing. A wafer probe tester is indexed from one die to the next for an uninterrupted testing of all die in the wafer subsequent to all die power up and stabilization.

Abstract: In one embodiment, a testing regimen is implemented to reduce test time. Specifically, a structure and method to power up and stabilize all die on the wafer prior to testing each die is implemented. More specifically, parallel powering schemes including die stabilization procedures are used to ready the wafer for testing. A wafer probe tester is indexed from one die to the next for an uninterrupted testing of all die in the wafer subsequent to all die power up and stabilization.

Abstract: Methods and apparatus for burn-in of integrated circuit (IC) dies at the wafer level. In one embodiment, a wafer is fabricated having an array of dies formed thereon wherein the dies are separated by scribe areas. Surrounding each die is one or more ring conductors which are electrically coupled to various circuits on the die via die bond pads. The wafer further includes a series of conductive pads located in an inactive region of the wafer. Electrically connecting the conductive pads to the ring conductors is a series of redundant scribe conductors. During burn-in, a burn-in indicating apparatus located on each die monitors burn-in parameters such as elapsed burn-in time. The indicating apparatus further records the elapsed burn-in time (or other parameter). The indicating apparatus may be subsequently interrogated to verify the burn-in time.