Patents by Inventor Andreas Arp
Andreas Arp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11256284Abstract: Disclosed aspects relate to a clock distribution network of a synchronous logic device. The synchronous logic device has sub-circuits having different clock domains. The clock domains form a hierarchical structure. The clock distribution network has a clock source to provide a global clock signal. A programmable delay line associated with a sub-circuit generates a local clock signal for the sub-circuit by delaying the signal. A global skew control circuit can manage clock skew between the local clock signals. The global skew control circuit may adjust a delay, determine initial operations for the delay lines, verify whether it is possible to perform the initial operations, and perform a correction operation. The correction operation can include correcting the control commands such that the corrected commands lead to the same change of skew adjustment between the local clocks.Type: GrantFiled: January 7, 2020Date of Patent: February 22, 2022Assignee: International Business Machines CorporationInventors: Andreas Arp, Andre Hertwig, Michael Koch, Matthias Ringe
-
Patent number: 10892744Abstract: The present invention provides a system and method of correcting duty cycle (DC) and compensating for active clock edge shift. In an embodiment, the system includes at least one control circuit to receive DCC control signals and to output at least one first adjustment signal, at least one second adjustment signal, at least one first correction signal, and at least one second correction signal, at least one adjustment circuit to change a DC value of an input clock signal, at least one correction circuit to compensate for a shift of an active clock edge of the input clock signal, and where one of the at least one adjustment circuit and the at least one correction circuit is to receive the input clock signal and wherein one of the at least one adjustment circuit and the at least one correction circuit is to transmit a corrected output clock signal.Type: GrantFiled: September 25, 2017Date of Patent: January 12, 2021Assignee: International Business Machines CorporationInventors: Michael Koch, Matthias Ringe, Andreas Arp, Fatih Cilek
-
Patent number: 10756714Abstract: Disclosed aspects relate to a clock distribution network of a synchronous logic device. The synchronous logic device comprises multiple sub-circuits belonging to different clock domains. The clock distribution network comprises a clock source operable for providing a global clock signal, at least one programmable delay line associated with a certain sub-circuit operable for generating a local clock signal for said sub-circuit by delaying the global clock signal or a signal derived therefrom and a global skew control circuit for managing clock skew between the local clock signals. The global skew control circuit is operable for managing clock skew between at least some local clock signals by regularly adjusting the delay caused by at least one programmable delay line when in a deskewing operating mode, and disabling adjusting the delays of the programmable delay lines when in a locked operating mode.Type: GrantFiled: May 28, 2019Date of Patent: August 25, 2020Assignee: International Business Machines CorporationInventors: Andreas Arp, Fatih Cilek, Michael Koch, Matthias Ringe
-
Patent number: 10651834Abstract: An apparatus of performing a clock skew adjustment between N clock signals. 2(N?1) skew sensors are configured as successive pairs k, each pair k having a first skew sensor and a second skew sensor. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. A skew controller performs the clock skew adjustment based on the first and second information.Type: GrantFiled: October 15, 2019Date of Patent: May 12, 2020Assignee: International Business Machines CorporationInventors: Andreas Arp, Fatih Cilek, Andre Hertwig, Michael Koch, Matthias Ringe
-
Publication number: 20200142443Abstract: Disclosed aspects relate to a clock distribution network of a synchronous logic device. The synchronous logic device has sub-circuits having different clock domains. The clock domains form a hierarchical structure. The clock distribution network has a clock source to provide a global clock signal. A programmable delay line associated with a sub-circuit generates a local clock signal for the sub-circuit by delaying the signal. A global skew control circuit can manage clock skew between the local clock signals. The global skew control circuit may adjust a delay, determine initial operations for the delay lines, verify whether it is possible to perform the initial operations, and perform a correction operation. The correction operation can include correcting the control commands such that the corrected commands lead to the same change of skew adjustment between the local clocks.Type: ApplicationFiled: January 7, 2020Publication date: May 7, 2020Inventors: Andreas Arp, Andre Hertwig, Michael Koch, Matthias Ringe
-
Patent number: 10564664Abstract: Disclosed aspects relate to a clock distribution network of a synchronous logic device. The synchronous logic device has sub-circuits having different clock domains. The clock domains form a hierarchical structure. The clock distribution network has a clock source to provide a global clock signal. A programmable delay line associated with a sub-circuit generates a local clock signal for the sub-circuit by delaying the signal. A global skew control circuit can manage clock skew between the local clock signals. The global skew control circuit may adjust a delay, determine initial operations for the delay lines, verify whether it is possible to perform the initial operations, and perform a correction operation. The correction operation can include correcting the control commands such that the corrected commands lead to the same change of skew adjustment between the local clocks.Type: GrantFiled: May 11, 2017Date of Patent: February 18, 2020Assignee: International Business Machines CorporationInventors: Andreas Arp, Andre Hertwig, Michael Koch, Matthias Ringe
-
Publication number: 20200044636Abstract: An apparatus of performing a clock skew adjustment between N clock signals. 2(N?1) skew sensors are configured as successive pairs k, each pair k having a first skew sensor and a second skew sensor. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. A skew controller performs the clock skew adjustment based on the first and second information.Type: ApplicationFiled: October 15, 2019Publication date: February 6, 2020Inventors: Andreas Arp, Fatih Cilek, Andre Hertwig, Michael Koch, Matthias Ringe
-
Patent number: 10469063Abstract: An apparatus of performing a clock skew adjustment between at least first and second clock signals includes first and second skew sensors and a skew controller. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. Each of the first and second information varies depending on the clock skew. The skew controller performs the clock skew adjustment based on the first and second information.Type: GrantFiled: March 22, 2019Date of Patent: November 5, 2019Assignee: International Business Machines CorporationInventors: Andreas Arp, Fatih Cilek, Andre Hertwig, Michael Koch, Matthias Ringe
-
Publication number: 20190280680Abstract: Disclosed aspects relate to a clock distribution network of a synchronous logic device. The synchronous logic device comprises multiple sub-circuits belonging to different clock domains. The clock distribution network comprises a clock source operable for providing a global clock signal, at least one programmable delay line associated with a certain sub-circuit operable for generating a local clock signal for said sub-circuit by delaying the global clock signal or a signal derived therefrom and a global skew control circuit for managing clock skew between the local clock signals. The global skew control circuit is operable for managing clock skew between at least some local clock signals by regularly adjusting the delay caused by at least one programmable delay line when in a deskewing operating mode, and disabling adjusting the delays of the programmable delay lines when in a locked operating mode.Type: ApplicationFiled: May 28, 2019Publication date: September 12, 2019Inventors: Andreas Arp, Fatih Cilek, Michael Koch, Matthias Ringe
-
Publication number: 20190222206Abstract: An apparatus of performing a clock skew adjustment between at least first and second clock signals includes first and second skew sensors and a skew controller. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. Each of the first and second information varies depending on the clock skew. The skew controller performs the clock skew adjustment based on the first and second information.Type: ApplicationFiled: March 22, 2019Publication date: July 18, 2019Inventors: Andreas Arp, Fatih Cilek, Andre Hertwig, Michael Koch, Matthias Ringe
-
Patent number: 10355683Abstract: The present invention provides a system and method of correcting duty cycle (DC) and compensating for active clock edge shift. In an embodiment, the system includes at least one control circuit to receive DCC control signals and to output at least one first adjustment signal, at least one second adjustment signal, at least one first correction signal, and at least one second correction signal, at least one adjustment circuit to change a DC value of an input clock signal, at least one correction circuit to compensate for a shift of an active clock edge of the input clock signal, and where one of the at least one adjustment circuit and the at least one correction circuit is to receive the input clock signal and wherein one of the at least one adjustment circuit and the at least one correction circuit is to transmit a corrected output clock signal.Type: GrantFiled: December 27, 2017Date of Patent: July 16, 2019Assignee: International Business Machines CorporationInventors: Michael Koch, Matthias Ringe, Andreas Arp, Fatih Cilek
-
Patent number: 10348278Abstract: An apparatus of performing a clock skew adjustment between at least first and second clock signals includes first and second skew sensors and a skew controller. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. Each of the first and second information varies depending on the clock skew. The skew controller performs the clock skew adjustment based on the first and second information.Type: GrantFiled: July 17, 2018Date of Patent: July 9, 2019Assignee: International Business Machines CorporationInventors: Andreas Arp, Fatih Cilek, Andre Hertwig, Michael Koch, Matthias Ringe
-
Patent number: 10348279Abstract: Disclosed aspects relate to a clock distribution network of a synchronous logic device. The synchronous logic device comprises multiple sub-circuits belonging to different clock domains. The clock distribution network comprises a clock source operable for providing a global clock signal, at least one programmable delay line associated with a certain sub-circuit operable for generating a local clock signal for said sub-circuit by delaying the global clock signal or a signal derived therefrom and a global skew control circuit for managing clock skew between the local clock signals. The global skew control circuit is operable for managing clock skew between at least some local clock signals by regularly adjusting the delay caused by at least one programmable delay line when in a deskewing operating mode, and disabling adjusting the delays of the programmable delay lines when in a locked operating mode.Type: GrantFiled: May 11, 2017Date of Patent: July 9, 2019Assignee: International Business Machines CorporationInventors: Andreas Arp, Fatih Cilek, Michael Koch, Matthias Ringe
-
Patent number: 10312892Abstract: A circuit for measuring a transition time of a digital signal may be provided. The circuit comprises a window detector comprising a comparator circuitry arranged for generating a first signal based on comparing said digital signal with a first reference voltage and for generating a second signal based on comparing said digital signal with a second reference voltage. Additionally, the circuit comprises a time-difference-to-digital converter operable for converting a delay between an edge of said first signal and an edge of said second signal into a digital value, said digital value characterizing said transition time of said digital signal.Type: GrantFiled: January 31, 2017Date of Patent: June 4, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andreas Arp, Fatih Cilek, Michael V. Koch, Matthias Ringe
-
Patent number: 10263606Abstract: A circuit for measuring a transition time of a digital signal may be provided. The circuit comprises a window detector comprising a comparator circuitry arranged for generating a first signal based on comparing said digital signal with a first reference voltage and for generating a second signal based on comparing said digital signal with a second reference voltage. Additionally, the circuit comprises a time-difference-to-digital converter operable for converting a delay between an edge of said first signal and an edge of said second signal into a digital value, said digital value characterizing said transition time of said digital signal.Type: GrantFiled: October 25, 2017Date of Patent: April 16, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andreas Arp, Fatih Cilek, Michael V. Koch, Matthias Ringe
-
Publication number: 20190097618Abstract: The present invention provides a system and method of correcting duty cycle (DC) and compensating for active clock edge shift. In an embodiment, the system includes at least one control circuit to receive DCC control signals and to output at least one first adjustment signal, at least one second adjustment signal, at least one first correction signal, and at least one second correction signal, at least one adjustment circuit to change a DC value of an input clock signal, at least one correction circuit to compensate for a shift of an active clock edge of the input clock signal, and where one of the at least one adjustment circuit and the at least one correction circuit is to receive the input clock signal and wherein one of the at least one adjustment circuit and the at least one correction circuit is to transmit a corrected output clock signal.Type: ApplicationFiled: December 27, 2017Publication date: March 28, 2019Inventors: Michael Koch, Matthias Ringe, Andreas Arp, Fatih Cilek
-
Publication number: 20190097617Abstract: The present invention provides a system and method of correcting duty cycle (DC) and compensating for active clock edge shift. In an embodiment, the system includes at least one control circuit to receive DCC control signals and to output at least one first adjustment signal, at least one second adjustment signal, at least one first correction signal, and at least one second correction signal, at least one adjustment circuit to change a DC value of an input clock signal, at least one correction circuit to compensate for a shift of an active clock edge of the input clock signal, and where one of the at least one adjustment circuit and the at least one correction circuit is to receive the input clock signal and wherein one of the at least one adjustment circuit and the at least one correction circuit is to transmit a corrected output clock signal.Type: ApplicationFiled: September 25, 2017Publication date: March 28, 2019Inventors: Michael Koch, Matthias Ringe, Andreas Arp, Fatih Cilek
-
Publication number: 20180331676Abstract: Disclosed aspects relate to a clock distribution network of a synchronous logic device. The synchronous logic device comprises multiple sub-circuits belonging to different clock domains. The clock distribution network comprises a clock source operable for providing a global clock signal, at least one programmable delay line associated with a certain sub-circuit operable for generating a local clock signal for said sub-circuit by delaying the global clock signal or a signal derived therefrom and a global skew control circuit for managing clock skew between the local clock signals. The global skew control circuit is operable for managing clock skew between at least some local clock signals by regularly adjusting the delay caused by at least one programmable delay line when in a deskewing operating mode, and disabling adjusting the delays of the programmable delay lines when in a locked operating mode.Type: ApplicationFiled: May 11, 2017Publication date: November 15, 2018Inventors: Andreas Arp, Fatih Cilek, Michael Koch, Matthias Ringe
-
Publication number: 20180329448Abstract: Disclosed aspects relate to a clock distribution network of a synchronous logic device. The synchronous logic device has sub-circuits having different clock domains. The clock domains form a hierarchical structure. The clock distribution network has a clock source to provide a global clock signal. A programmable delay line associated with a sub-circuit generates a local clock signal for the sub-circuit by delaying the signal. A global skew control circuit can manage clock skew between the local clock signals. The global skew control circuit may adjust a delay, determine initial operations for the delay lines, verify whether it is possible to perform the initial operations, and perform a correction operation. The correction operation can include correcting the control commands such that the corrected commands lead to the same change of skew adjustment between the local clocks.Type: ApplicationFiled: May 11, 2017Publication date: November 15, 2018Inventors: Andreas Arp, Andre Hertwig, Michael Koch, Matthias Ringe
-
Publication number: 20180323773Abstract: An apparatus of performing a clock skew adjustment between at least first and second clock signals includes first and second skew sensors and a skew controller. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. Each of the first and second information varies depending on the clock skew. The skew controller performs the clock skew adjustment based on the first and second information.Type: ApplicationFiled: July 17, 2018Publication date: November 8, 2018Inventors: Andreas Arp, Fatih Cilek, Andre Hertwig, Michael Koch, Matthias Ringe