Patents by Inventor Andreas Augustin

Andreas Augustin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200373259
    Abstract: Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a conductive cavity antenna over the first conductive layer and substrate. The conductive cavity antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the conductive cavity antenna, first conductive layer, and substrate. The conductive cavity extends vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Inventors: Sonja KOLLER, Kilian ROTH, Josef HAGN, Andreas WOLTER, Andreas AUGUSTIN
  • Publication number: 20200365996
    Abstract: Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a cavity resonator antenna over the first conductive layer and substrate. The cavity resonator antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the cavity resonator antenna, first conductive layer, and substrate. The conductive cavity may extend vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 19, 2020
    Inventors: Kilian ROTH, Sonja KOLLER, Josef HAGN, Andreas WOLTER, Andreas AUGUSTIN
  • Publication number: 20200227388
    Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 16, 2020
    Inventors: Bernd Waidhas, Georg Seidemann, Thomas Wagner, Andreas Wolter, Andreas Augustin, Sonja Koller, Thomas Ort, Reinhard Mahnkopf
  • Publication number: 20200185490
    Abstract: The present disclosure is directed to systems and methods for fabricating a semiconductor inductor that includes a coil deposited on a stop layer that is deposited on a sacrificial substrate. The semiconductor inductor may be fabricated on a silicon wafer and singulated. The sacrificial substrate beneficially provides structural support for the singulated semiconductor inductor. The singulated semiconductor inductor advantageously requires minimal active die surface area. The removal of the sacrificial substrate after coupling to the active die beneficially reduces the overall thickness (or height) of the semiconductor package, providing a decided advantage in low profile, portable, electronic devices.
    Type: Application
    Filed: June 30, 2017
    Publication date: June 11, 2020
    Applicant: INTEL IP CORPORATION
    Inventors: Georg Seidemann, Bernd WAIDHAS, Thomas WAGNER, Andreas WOLTER, Andreas AUGUSTIN
  • Publication number: 20200147417
    Abstract: A device for supplying breathing gas to a user includes: a mask having a breathing opening; and a bag having a bag opening that is connected to the breathing opening in fluid communication, wherein the device further includes an adjustable exhalation valve, wherein the adjustable exhalation valve is in fluid communication with the bag. Thus, the device for supplying breathing gas to a user provides protection against hyperventilation, toxic gases and smoke.
    Type: Application
    Filed: November 1, 2019
    Publication date: May 14, 2020
    Applicant: Airbus Operations GmbH
    Inventors: Patrick Bricard, Joerg Cremers, Timo Martin, Andreas Bezold, Norbert Augustin
  • Publication number: 20200144723
    Abstract: A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.
    Type: Application
    Filed: March 31, 2017
    Publication date: May 7, 2020
    Inventors: Andreas Augustin, Sonja Koller, Bernd Waidhas, Georg Seidemann, Andreas Wolter, Stephan Stoeckl, Thomas Wagner, Josef Hagn
  • Publication number: 20200111607
    Abstract: A recess in a die backside surface occupies a footprint that accommodates an inductor coil that is formed in metallization above an active surface of the die. Less semiconductive material is therefore close to the inductor coil. A ferromagnetic material is formed in the recess, or a ferromagnetic material is formed on a dielectric layer above the inductor coil. The recess may extend across a die that allows the die to be deflected at the recess.
    Type: Application
    Filed: March 30, 2017
    Publication date: April 9, 2020
    Inventors: Andreas Augustin, Bernd Waidhas, Sonja Koller, Reinhard Mahnkopf, Georg Seidemann
  • Patent number: 10597826
    Abstract: The invention relates to a sleeper pad (1) for fastening to at least one outer surface (3) of a railway sleeper (4) facing a ballast bed (2), the sleeper pad (1) including or consisting of at least one damping layer (5), wherein the damping layer (5) has an EPM index in the range from 10 to 25%, preferably in the range from 10 to 20% when carrying out a load test.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: March 24, 2020
    Assignee: Getzner Werkstoffe Holding GmbH
    Inventors: Andreas Augustin, Harald Loy, Stefan Potocan
  • Patent number: 10560125
    Abstract: This disclosure relates to a data processing device, comprising: a digital front end (DFE) configured to convert an antenna signal to digital data, wherein the digital data comprises a plurality of data symbols; a baseband (BB) circuitry configured to process the digital data in baseband; and a digital interface between the DFE and the BB circuitry, wherein the DFE comprises a data compression circuitry configured to compress the plurality of data symbols for use in transmission via the digital interface to the BB circuitry.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: February 11, 2020
    Assignee: Intel Corporation
    Inventors: Shilpa Talwar, Christian Drewes, Andreas Augustin, Peter Noest, Stefan Mueller-Weinfurtner, Oner Orhan, Hosein Nikopour, Junyoung Nam
  • Publication number: 20200006272
    Abstract: Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Andreas Augustin, Georg Seidemann, Thomas Wagner, Bernd Waidhas
  • Publication number: 20190341371
    Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.
    Type: Application
    Filed: July 18, 2019
    Publication date: November 7, 2019
    Inventors: Bernd Waidhas, Georg Seidemann, Andreas Augustin, Laurent Millou, Andreas Wolter, Reinhard Mahnkopf, Stephan Stoeckl, Thomas Wagner
  • Publication number: 20190304922
    Abstract: A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 3, 2019
    Inventors: Saravana Maruthamuthu, Thomas Ort, Andreas Wolter, Andreas Augustin, Veronica Sciriha, Bernd Waidhas
  • Publication number: 20190272950
    Abstract: A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.
    Type: Application
    Filed: March 2, 2018
    Publication date: September 5, 2019
    Inventors: Saravana Maruthamuthu, Andreas Augustin, Andreas Wolter
  • Patent number: 10403602
    Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 3, 2019
    Assignee: Intel IP Corporation
    Inventors: Bernd Waidhas, Georg Seidemann, Andreas Augustin, Laurent Millou, Andreas Wolter, Reinhard Mahnkopf, Stephan Stoeckl, Thomas Wagner
  • Publication number: 20190252792
    Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.
    Type: Application
    Filed: February 9, 2018
    Publication date: August 15, 2019
    Inventors: Saravana Maruthamuthu, Bernd Waidhas, Andreas Augustin, Georg Seidemann
  • Publication number: 20190238163
    Abstract: This disclosure relates to a data processing device, comprising: a digital front end (DFE) configured to convert an antenna signal to digital data, wherein the digital data comprises a plurality of data symbols; a baseband (BB) circuitry configured to process the digital data in baseband; and a digital interface between the DFE and the BB circuitry, wherein the DFE comprises a data compression circuitry configured to compress the plurality of data symbols for use in transmission via the digital interface to the BB circuitry.
    Type: Application
    Filed: July 17, 2018
    Publication date: August 1, 2019
    Inventors: Shilpa Talwar, Christian Drewes, Andreas Augustin, Peter Noest, Stefan Mueller-Weinfurtner, Oner Orhan, Hosein Nikopour, Junyoung Nam
  • Patent number: 10301176
    Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel IP Corporation
    Inventors: Gerald Ofner, Thorsten Meyer, Reinhard Mahnkopf, Christian Geissler, Andreas Augustin
  • Publication number: 20190006318
    Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 3, 2019
    Inventors: Bernd Waidhas, Georg Seidemann, Andreas Augustin, Laurent Millou, Andreas Wolter, Reinhard Mahnkopf, Stephan Stoeckl, Thomas Wagner
  • Patent number: 10150668
    Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: December 11, 2018
    Assignee: Intel IP Corporation
    Inventors: Gerald Ofner, Thorsten Meyer, Reinhard Mahnkopf, Christian Geissler, Andreas Augustin
  • Patent number: 10122420
    Abstract: Apparatus and methods are provided for wireless communications between integrated circuits or integrated circuit dies of an electronic system. In an example, an apparatus can include a first integrated circuit die including a plurality of integrated circuit devices, a second integrated circuit die including a second plurality of integrated circuit devices, and a conductor device configured to wirelessly receive a signal from the first integrated circuit die, to conduct the signal from a first end of an electrical conductor of the conductor device to a second end of the electrical conductor, and to wirelessly transmit the signal to the second integrated circuit die from the second end of the electrical conductor.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: November 6, 2018
    Assignee: Intel IP Corporation
    Inventors: Thorsten Meyer, Andreas Augustin, Reinhard Golly, Peter Baumgartner