Abstract: A hybrid integrated circuit in a wafer level package for an implantable medical device includes one or more passive component windings formed, at least in part, along one or more routing layers of the package. The windings may be primary and secondary windings of a transformer, wherein all or part of a magnetic core thereof is embedded in a component layer of the wafer level package. If the core includes a part bonded to a surface of the package, that part of the core may be E-shaped with legs extending into the routing layers, and, in some cases, through the routing layers. Routing layers may be formed on both sides of the component layer to accommodate the transformer windings, in some instances.

Abstract: Arrays of planar solid state batteries are stacked in an aligned arrangement for subsequent separation into individual battery stacks. Prior to stacking, a redistribution layer (RDL) is formed over a surface of each wafer that contains an array; each RDL includes first and second groups of conductive traces, each of the first extending laterally from a corresponding positive battery contact, and each of the second extending laterally from a corresponding negative battery contact. Conductive vias, formed before or after stacking, ultimately couple together corresponding contacts of aligned batteries. If before, each via extends through a corresponding battery contact of each wafer and is coupled to a corresponding conductive layer that is included in another RDL formed over an opposite surface of each wafer. If after, each via extends through corresponding aligned conductive traces and, upon separation of individual battery stacks, becomes an exposed conductive channel of a corresponding battery stack.

Abstract: Various embodiments of a nuclear radiation particle power converter and method of forming such power converter are disclosed. In one or more embodiments, the power converter can include first and second electrodes, a three-dimensional current collector disposed between the first and second electrodes and electrically coupled to the first electrode, and a charge carrier separator disposed on at least a portion of a surface of the three-dimensional current collector. The power converter can also include a hole conductor layer disposed on at least a portion of the charge carrier separator and electrically coupled to the second electrode, and nuclear radiation-emitting material disposed such that at least one nuclear radiation particle emitted by the nuclear radiation-emitting material is incident upon the charge carrier separator.

Abstract: A hybrid integrated circuit in a wafer level package for an implantable medical device includes one or more passive component windings formed, at least in part, along one or more routing layers of the package. The windings may be primary and secondary windings of a transformer, wherein all or part of a magnetic core thereof is embedded in a component layer of the wafer level package. If the core includes a part bonded to a surface of the package, that part of the core may be E-shaped with legs extending into the routing layers, and, in some cases, through the routing layers. Routing layers may be formed on both sides of the component layer to accommodate the transformer windings, in some instances.

Abstract: Systems, apparatus and methods configured to facilitate pairing an implantable device with a remote device using a near field communication (NFC) device attached to the implantable device are presented. In an aspect, an implantable device assembly includes an implantable device and an NFC component externally attached to the implantable device. The NFC component is configured to transmit identification information associated with the implantable device to a reader device using NFC protocol. Transmission is in response to a received request signal.

Abstract: A hybrid integrated circuit in a wafer level package for an implantable medical device includes one or more passive component windings formed, at least in part, along one or more routing layers of the package. The windings may be primary and secondary windings of a transformer, wherein all or part of a magnetic core thereof is embedded in a component layer of the wafer level package. If the core includes a part bonded to a surface of the package, that part of the core may be E-shaped with legs extending into the routing layers, and, in some cases, through the routing layers. Routing layers may be formed on both sides of the component layer to accommodate the transformer windings, in some instances.

Abstract: A hybrid integrated circuit in a wafer level package for an implantable medical device includes one or more passive component windings formed, at least in part, along one or more routing layers of the package. The windings may be primary and secondary windings of a transformer, wherein all or part of a magnetic core thereof is embedded in a component layer of the wafer level package. If the core includes a part bonded to a surface of the package, that part of the core may be E-shaped with legs extending into the routing layers, and, in some cases, through the routing layers. Routing layers may be formed on both sides of the component layer to accommodate the transformer windings, in some instances.

Abstract: Arrays of planar solid state batteries are stacked in an aligned arrangement for subsequent separation into individual battery stacks. Prior to stacking, a redistribution layer (RDL) is formed over a surface of each wafer that contains an array; each RDL includes first and second groups of conductive traces, each of the first extending laterally from a corresponding positive battery contact, and each of the second extending laterally from a corresponding negative battery contact. Conductive vias, formed before or after stacking, ultimately couple together corresponding contacts of aligned batteries. If before, each via extends through a corresponding battery contact of each wafer and is coupled to a corresponding conductive layer that is included in another RDL formed over an opposite surface of each wafer. If after, each via extends through corresponding aligned conductive traces and, upon separation of individual battery stacks, becomes an exposed conductive channel of a corresponding battery stack.

Abstract: The present invention describes systems and methods for providing high-density capacitors. An exemplary embodiment of the present invention provides a high-density capacitor system comprising a substrate and a porous conductive layer formed on the substrate, wherein the porous conductive layer is formed in accordance with a predetermined pattern. Furthermore, the high-density capacitor system includes a dielectric material formed on the porous conductive layer and a second conductive layer formed on the dielectric material. Additionally, the high-density capacitor system includes a plurality of conductive pads configured in communication with the second conductive layer.

Abstract: The present invention describes systems and methods for providing high-density capacitors. An exemplary embodiment of the present invention provides a high-density capacitor system comprising a substrate and a porous conductive layer formed on the substrate, wherein the porous conductive layer is formed in accordance with a predetermined pattern. Furthermore, the high-density capacitor system includes a dielectric material formed on the porous conductive layer and a second conductive layer formed on the dielectric material. Additionally, the high-density capacitor system includes a plurality of conductive pads configured in communication with the second conductive layer.

Abstract: The present invention describes systems and methods for fabricating high-density capacitors. An exemplary embodiment of the present invention provides a method for fabricating a high-density capacitor system including the steps of providing a substrate and depositing a nanoelectrode particulate paste layer onto the substrate. The method for fabricating a high-density capacitor system further includes sintering the nanoelectrode particulate paste layer to form a bottom electrode. Additionally, the method for fabricating a high-density capacitor system includes depositing a dielectric material onto the bottom electrode with an atomic layer deposition process. Furthermore, the method for fabricating a high-density capacitor system includes depositing a conductive material on the dielectric material to form a top electrode.

Abstract: An overvoltage protection device is formed in a semiconductor substrate having a plurality of doped regions for forming semiconductor devices. The overvoltage protection device is adapted to draw current away from a device to be protected from excess voltage and has a switchable device having a terminal adapted to be coupled to a potential source of excess voltage and to the semiconductor substrate for drawing current away from the potential source of excess voltage when the switchable device is triggered, and for directing the current to the semiconductor substrate. A Zener diode is coupled to a second terminal of the switchable device to trigger the switchable device to a conducting state. The Zener diode is formed in the same doped region of the substrate as the trigger of the switchable device.

Abstract: Method and apparatus are provided for fabricating a planar transformer assembly for use in an implantable medical device. The planar transformer assembly includes a board, a first core, and a second core. The board has a first side, a second side, and an embedded winding, wherein the embedded winding includes a primary winding and a secondary winding and is at least partially embedded in the board between the first and second sides.

Abstract: Methods and apparatus are provided for an accelerometer. The apparatus includes first, second, and third substrates. The first substrate includes the first plate of a first capacitor. The second substrate includes a moveable mass that is coupled to the second substrate by at least one spring. The moveable mass is the second plate of the first capacitor and the first plate of a second capacitor. The third substrate includes the second plate of the second capacitor. The moveable mass is prevented from moving in any direction where the at least one spring is inelastically flexed. The first substrate couples to the second substrate. The third substrate couples to the second substrate. The method includes forming a moveable mass in a substrate. The moveable mass is formed having a plurality of springs coupling the moveable mass to the substrate. The moveable mass is released using a dry etch.

Abstract: Method and apparatus are provided for fabricating a planar transformer assembly for use in an implantable medical device. The planar transformer assembly includes a board, a first core, and a second core. The board has a first side, a second side, and an embedded winding, wherein the embedded winding includes a primary winding and a secondary winding and is at least partially embedded in the board between the first and second sides.

Abstract: Methods and apparatus are provided for an accelerometer. The apparatus includes first, second, and third substrates. The first substrate includes the first plate of a first capacitor. The second substrate includes a moveable mass that is coupled to the second substrate by at least one spring. The moveable mass is the second plate of the first capacitor and the first plate of a second capacitor. The third substrate includes the second plate of the second capacitor. The moveable mass is prevented from moving in any direction where the at least one spring is inelastically flexed. The first substrate couples to the second substrate. The third substrate couples to the second substrate. The method includes forming a moveable mass in a substrate. The moveable mass is formed having a plurality of springs coupling the moveable mass to the substrate. The moveable mass is released using a dry etch.

Abstract: A flip-chip package comprises a substrate having at least one layer and a component flip-chip mounted to the substrate, the component having a field termination ring. The flip-chip package further comprises a shield plane interposed between the at least one layer of substrate and the field termination ring.

Abstract: In one embodiment, a testing regimen is implemented to reduce test time. Specifically, a structure and method to power up and stabilize all die on the wafer prior to testing each die is implemented. More specifically, parallel powering schemes including die stabilization procedures are used to ready the wafer for testing. A wafer probe tester is indexed from one die to the next for an uninterrupted testing of all die in the wafer subsequent to all die power up and stabilization.

Abstract: A flip-chip package comprises a substrate having at least one layer and a component flip-chip mounted to the substrate, the component having a field termination ring. The flip-chip package further comprises a shield plane interposed between the at least one layer of substrate and the field termination ring.

Abstract: An overvoltage protection device is formed in a semiconductor substrate having a plurality of doped regions for forming semiconductor devices. The overvoltage protection device is adapted to draw current away from a device to be protected from excess voltage and has a switchable device having a terminal adapted to be coupled to a potential source of excess voltage and to the semiconductor substrate for drawing current away from the potential source of excess voltage when the switchable device is triggered, and for directing the current to the semiconductor substrate.