Patents by Inventor Andreas Goebel

Andreas Goebel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240093537
    Abstract: Described is a vehicle door actuating apparatus (100). The vehicle door actuating apparatus (100) includes an actuating surface (106), a sensor (140), such as an inductive sensor or switch, and a mechanism for transmitting a compressive force applied by a user to the actuating surface (106) into a movement that is detectable by the sensor. The mechanism includes a first component (111) or a first component group on which the switch (140) is at least partially fixed and a transmission element (120) that is pivotally arranged on the first component (111) or the first component group. The transmission element (120) is pivotable between a home position in which the sensor (140) is not triggered by the transmission element (120) and an actuating position in which the sensor (140) is triggered by the transmission element (120). The transmission element (120) is movable relative to the actuating apparatus (102).
    Type: Application
    Filed: September 12, 2023
    Publication date: March 21, 2024
    Inventors: Zsolt WILKE, Andreas RUDOLF, Fritz GÖBEL, Martin WEID
  • Publication number: 20240072150
    Abstract: An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10?5-10?7 ?-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×1019 cm?3 and less than approximately 10?8 ?-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 1020 cm?3.
    Type: Application
    Filed: October 19, 2023
    Publication date: February 29, 2024
    Inventors: Paul A. Clifton, Andreas Goebel
  • Publication number: 20240030306
    Abstract: Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.
    Type: Application
    Filed: September 26, 2023
    Publication date: January 25, 2024
    Inventors: Walter A. Harrison, Paul A. Clifton, Andreas Goebel, R. Stockton Gaines
  • Publication number: 20240006532
    Abstract: A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.
    Type: Application
    Filed: September 11, 2023
    Publication date: January 4, 2024
    Inventors: Paul A. Clifton, Andreas Goebel
  • Patent number: 11843040
    Abstract: An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10?5-10?7 ?-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×1019 cm?3 and less than approximately 10?8 ?-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 1020 cm?3.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: December 12, 2023
    Assignee: Acorn Semi, LLC
    Inventors: Paul A. Clifton, Andreas Goebel
  • Patent number: 11804533
    Abstract: Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: October 31, 2023
    Assignee: Acorn Semi, LLC
    Inventors: Walter A. Harrison, Paul A. Clifton, Andreas Goebel, R. Stockton Gaines
  • Publication number: 20230344200
    Abstract: Tensile strained germanium is provided that can be sufficiently strained to provide a nearly direct band gap material or a direct band gap material. Compressively stressed or tensile stressed stressor materials in contact with germanium regions induce uniaxial or biaxial tensile strain in the germanium regions. Stressor materials may include silicon nitride or silicon germanium. The resulting strained germanium structure can be used to emit or detect photons including, for example, generating photons within a resonant cavity to provide a laser.
    Type: Application
    Filed: June 15, 2023
    Publication date: October 26, 2023
    Inventors: Paul A. Clifton, Andreas Goebel, R. Stockton Gaines
  • Patent number: 11791411
    Abstract: A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: October 17, 2023
    Assignee: Acorn Semi, LLC
    Inventors: Paul A. Clifton, Andreas Goebel
  • Publication number: 20230317814
    Abstract: An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10?5-10?7 ?-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×1019 cm?3 and less than approximately 10?8 ?-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 1020 cm?3.
    Type: Application
    Filed: November 10, 2020
    Publication date: October 5, 2023
    Inventors: Paul A. Clifton, Andreas Goebel
  • Patent number: 11728624
    Abstract: Tensile strained germanium is provided that can be sufficiently strained to provide a nearly direct band gap material or a direct band gap material. Compressively stressed or tensile stressed stressor materials in contact with germanium regions induce uniaxial or biaxial tensile strain in the germanium regions. Stressor materials may include silicon nitride or silicon germanium. The resulting strained germanium structure can be used to emit or detect photons including, for example, generating photons within a resonant cavity to provide a laser.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: August 15, 2023
    Inventors: Paul A. Clifton, Andreas Goebel, R. Stockton Gaines
  • Publication number: 20230207657
    Abstract: Techniques for reducing the specific contact resistance of metal - semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal - group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.
    Type: Application
    Filed: February 23, 2023
    Publication date: June 29, 2023
    Inventors: Walter A. Harrison, Paul A. Clifton, Andreas Goebel, R. Stockton Gaines
  • Patent number: 11610974
    Abstract: Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: March 21, 2023
    Assignee: Acorn Semi, LLC
    Inventors: Walter A. Harrison, Paul A. Clifton, Andreas Goebel, R. Stockton Gaines
  • Publication number: 20230006066
    Abstract: A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.
    Type: Application
    Filed: September 9, 2022
    Publication date: January 5, 2023
    Inventors: Paul A. Clifton, Andreas Goebel, Walter A. Harrison
  • Patent number: 11512809
    Abstract: A rotatable connection for a stand apparatus to be arranged in an operating room and including an adaptable stop mechanism which can be arranged between a first connection component and a second connection component mounted rotatably around a rotational axis relative to the first connection component and is configured to define at least two different relative rotational angles of the connection components or at least two different rotational ranges is provided. A carrier system or a stand apparatus having such a rotatable connection is also provided.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: November 29, 2022
    Assignee: Ondal Medical Systems GmbH
    Inventors: Stefan Oginski, Ronny Bauditz, Andreas Göbel, Annika Euler
  • Patent number: 11462643
    Abstract: A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: October 4, 2022
    Assignee: Acorn Semi, LLC
    Inventors: Paul A. Clifton, Andreas Goebel, Walter A. Harrison
  • Publication number: 20220237294
    Abstract: A method is provided for validating trustworthy data in a computer system which comprises a distributed repository network, a client system coupled to the repository network and a server system coupled to the repository network. The trustworthy data comprise data sets which are stored in a memory device of the first server system. A validation query message is generated on the client system, which validation query message is stored in the repository network and transferred to the server system. The server system transfers the validation query message for response to a trustworthy software component, which is executed in a trustworthy and secured environment of the server system. The trustworthy software component generates a validation reply message, which is stored in the repository network and transferred to the client system.
    Type: Application
    Filed: April 8, 2022
    Publication date: July 28, 2022
    Inventors: Andreas GOEBEL, Steffen JOSWIG, Josef PACKOWSKI
  • Publication number: 20220229700
    Abstract: A method is provided for securely executing a workflow in a computer system which comprises at least a distributed repository network and a number of client systems that are operatively coupled or operatively couplable to this repository network. A model of the workflow is stored in the repository network. The workflow model comprises a number of workflow steps, and execution conditions, events, tasks and notifications are stored in the workflow model for each workflow step. To execute the workflow, a workflow instance is generated from the workflow model and is stored in the repository network. The client systems execute the workflow instance stored in the repository network.
    Type: Application
    Filed: April 8, 2022
    Publication date: July 21, 2022
    Inventors: Andreas GOEBEL, Steffen JOSWIG, Josef PACKOWSKI
  • Publication number: 20220223735
    Abstract: A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 14, 2022
    Inventors: Paul A. Clifton, Andreas Goebel
  • Publication number: 20220173575
    Abstract: Tensile strained germanium is provided that can be sufficiently strained to provide a nearly direct band gap material or a direct band gap material. Compressively stressed or tensile stressed stressor materials in contact with germanium regions induce uniaxial or biaxial tensile strain in the germanium regions. Stressor materials may include silicon nitride or silicon germanium. The resulting strained germanium structure can be used to emit or detect photons including, for example, generating photons within a resonant cavity to provide a laser.
    Type: Application
    Filed: February 15, 2022
    Publication date: June 2, 2022
    Inventors: Paul A. Clifton, Andreas Goebel, R. Stockton Gaines
  • Patent number: 11322615
    Abstract: A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: May 3, 2022
    Assignee: Acorn Semi, LLC
    Inventors: Paul A. Clifton, Andreas Goebel