Abstract: A process and an apparatus are described for the treatment of wafers, in particular for the thinning of wafers. A wafer with a carrier layer and an interlayer arranged between the carrier layer and the wafer is also described, in which the interlayer is a plasmapolymeric layer that adheres to the wafer and adheres more strongly to the carrier layer than to the wafer.

Abstract: A method of controlling an analog signal in an integrated circuit includes generating a first control signal having a first predetermined duration within the integrated circuit. The first control signal is configured to cause the analog signal to have a first signal level. The first signal level is compared to a level of a target signal. A second control signal is generated within the integrated circuit based on a result of the comparison. The second control signal is configured to cause the analog signal to have a second signal level. The second control signal has a second predetermined duration that is different than the first predetermined duration.

Abstract: An integrated circuit includes a chain of delay elements, a first phase detector, and a controller. The chain of delay elements is configured to delay an input clock signal for providing an output clock signal phase shifted with respect to the input clock signal by a selected value. The first phase detector is configured to provide a common control signal to each delay element based on a phase difference between the input clock signal and a signal output from one of the delay elements to adjust a delay of each delay element. The controller is configured to provide an independent control signal to each delay element to individually adjust the delay of each delay element such that the delay of each delay element is equal.

Abstract: The present patent application relates to a wafer support arrangement, comprising a wafer (1), a support layer system (5, 6) and a separating layer (4), which is arranged between the support layer system (5, 6) and the wafer (1), wherein the support layer system (5, 6) (i) comprises a support layer (6) and (ii) a layer (5) from a through hardened, partially hardened or hardenable elastomer material on the separating layer side or consists of these two layers and wherein the separating layer (4) (iii) is a plasma polymer layer and (iv) the adhesive bond between the support layer system (5, 6) and the separating layer (4), after the elastomer material has through hardened, is greater than the adhesive bond between the wafer (1) and the separating layer (4).

Abstract: A buffer component for a memory module having a plurality of memory components includes item of access information in accordance with a data transmission protocol, the address, clock, control and command signals depending on the access information, a second data interface for driving a clock signal and address and command signals to the plurality of memory components and for driving a control signal to a group of the plurality of memory components in accordance with a signaling protocol, wherein an activation of the memory components and an acceptance of the address and command signals are effected in a manner dependent on the control signals, and a control unit which applies the address and command signals to the plurality of memory components during a first clock period of the clock signal and applies the control signal for activating the group of the plurality of memory components to the group of the plurality of memory components to be activated when address and command signals are present, in a succeedin

Abstract: A method of calibrating an output driver circuit includes providing a comparator to compare drive signals to a reference signal. The reference signal is adjusted to compensate an offset voltage of the comparator. A first drive signal is compared to the adjusted reference signal by the comparator. The first drive signal is adjusted to match the adjusted reference signal, thereby calibrating a first impedance of the output driver circuit.

Abstract: An integrated circuit includes a chain of delay elements, a first phase detector, and a controller. The chain of delay elements is configured to delay an input clock signal for providing an output clock signal phase shifted with respect to the input clock signal by a selected value. The first phase detector is configured to provide a common control signal to each delay element based on a phase difference between the input clock signal and a signal output from one of the delay elements to adjust a delay of each delay element. The controller is configured to provide an independent control signal to each delay element to individually adjust the delay of each delay element such that the delay of each delay element is equal.

Abstract: The invention describes a method for adjusting signal propagation times in a memory system in which a controller is connected to at least one memory chip via a plurality of connecting lines for the purpose of transmitting control and data signals and at least one time reference signal. In line with the invention, the propagation time differences between connecting lines are ascertained from the result of echo measurements. To this end a respective transmitted pulse is applied to one end, selected as the transmission end, of the connecting lines in question, while the other end of the connecting lines in question is respectively terminated with a reflective termination. At the transmission end, the echo time which elapses between one edge of the transmitted pulse and the appearance of this edge's echo reflected from the other end is measured. On the basis of the ascertained propagation time differences, regulatable delay devices are set in order to compensate for these propagation time differences.

Abstract: A method of controlling an analog signal in an integrated circuit includes generating a first control signal having a first predetermined duration within the integrated circuit. The first control signal is configured to cause the analog signal to have a first signal level. The first signal level is compared to a level of a target signal. A second control signal is generated within the integrated circuit based on a result of the comparison. The second control signal is configured to cause the analog signal to have a second signal level. The second control signal has a second predetermined duration that is different than the first predetermined duration.

Abstract: A process and an apparatus are described for the treatment of wafers, in particular for the thinning of wafers. A wafer with a carrier layer and an interlayer arranged between the carrier layer and the wafer is also described, in which the interlayer is a plasmapolymeric layer that adheres to the wafer and adheres more strongly to the carrier layer than to the wafer.

Abstract: One embodiment of the invention relates to a RAM memory circuit. A memory circuit includes a multiplicity of memory cells which can be selectively addressed, I/O circuitry for data; a clock input for receiving a system clock signal; a reception sampling circuit for sampling the received data using a reception strobe signal; and a reception strobe signal generating device which internally generates the reception strobe signal with synchronization with the received system clock signal.

Abstract: A process and an apparatus are described for the treatment of wafers, in particular for the thinning of wafers. A wafer with a carrier layer and an interlayer arranged between the carrier layer and the wafer is also described, in which the interlayer is a plasmapolymeric layer that adheres to the wafer and adheres more strongly to the carrier layer than to the wafer.

Abstract: A method is provided for adapting the phase relationship between a clock signal and a strobe signal for accepting write data to be transmitted into a memory circuit, a write command signal being transmitted to the memory circuit in a manner synchronized with the clock signal, a write data signal being transmitted synchronously with the strobe signal, a phase offset between the transmitted clock signal and the transmitted strobe signal being set such that the write data are reliably accepted in the memory circuit.

Abstract: A Phase shifter for generating a phase-shifted, in particular phase-delayed, output signal from an input signal is disclosed. In one embodiment, the phase shifter includes a first delay line and at least one further delay line with respectively cascaded delay elements that form a U-shaped signal path along which at least one delay element is adapted to be controlled to be optionally opening or closing. A phase discriminator located at the input side of which a clock signal and a signal from one of the delay lines can be applied, and the output side of which is connected with a respective control input of the delay elements. The clock signal can also be applied to the first delay line, so that a feedback loop is formed by the phase discriminator and at least one of the delay lines. The input signal can be applied to the delay line whose signal output is not connected with the phase discriminator, and the output signal can be output therefrom.

Abstract: The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and command and address signals to the memory chips and data signals to and from the memory chips via a clock, address, command and data bus inside the module and which forms an interface to an external primary memory bus. The semiconductor memory module has an even number of buffer chips arranged on it and all of the memory chips are connected to two respective buffer chips at least by one signal line type from a signal group and just to one of the two buffer chips by the remaining signal lines from the group.

Abstract: The invention relates to a DLL circuit for providing an adjustable time delay of a periodic input signal, said circuit having controllable delay elements which are connected in series and form a delay chain, having a phase detector in order to generate a control signal on the basis of the periodic input signal and a periodic signal which has been delayed by the delay chain, the delay of each of the delay elements being adjusted on the basis of the control signal, and having a selection unit which is respectively connected to one of the delay elements in order to apply an output signal from one of the delay elements to an output of the DLL circuit on the basis of a selection variable which has been provided, and a compensation circuit which modifies the selection signal such that an additional delay (which is caused at least by the selection unit) between the periodic input signal and the output signal from the DLL circuit is compensated for.

Abstract: A memory module, which enables a module-internal, cross-chip electrical functional test of a plurality of integrated memory chips arranged on a printed circuit board of the memory module, includes a test device arranged separately from the memory chips on the printed circuit board. The test device relies on a clock signal provided by an external tester and generates the test signals required for carrying out the functional test and forwards the signals via control lines, address lines, data lines, and lines for the selection of individual memory chips to the latter. The partial integration of test functions into the test device enables a greater independence with respect to external electromagnetic interference influences without the space requirement of the memory module being increased overmuch.

Abstract: A binaural communication link between two hearing devices is established via at least one wire (7w) and a conductor, which is formed by individual's body (7B).

Abstract: The invention relates to a semiconductor memory module having a plurality of memory chips arranged next to one another in a row. The memory module has a module-internal clock, command/address and data bus which transfers clock signal, command and address signals and also data signals from a memory controller device to the memory chips and data signals from the memory chips to the memory controller device. The memory module has respective clock, command/address and data signal lines. The clock signal lines comprise two differential clock signal lines which, at their end opposite to the memory controller device are either open or connected to one another by a short-circuiting bridge. The memory chips, during a write operation, synchronize the write data with the clock signal running from the memory controller device to the end of the clock signal line and, during a read operation, output the read data synchronously with the clock signal reflected from the open or short-circuited end of the clock signal lines.

Abstract: A Phase shifter for generating a phase-shifted, in particular phase-delayed, output signal from an input signal is disclosed. In one embodiment, the phase shifter includes a first delay line and at least one further delay line with respectively cascaded delay elements that form a U-shaped signal path along which at least one delay element is adapted to be controlled to be optionally opening or closing. A phase discriminator located at the input side of which a clock signal and a signal from one of the delay lines can be applied, and the output side of which is connected with a respective control input of the delay elements. The clock signal can also be applied to the first delay line, so that a feedback loop is formed by the phase discriminator and at least one of the delay lines. The input signal can be applied to the delay line whose signal output is not connected with the phase discriminator, and the output signal can be output therefrom.