Abstract: The invention relates to a compact low-pressure discharge lamp (1) comprising a discharge vessel (3) with electrodes and power supply leads (7), a discharge vessel mount on which the discharge vessel is mounted, and a cap (10), which comprises a housing (11), connecting contacts (12) and a mounting plate (13) with a ballast apparatus (15), with the mounting plate being fitted with the ballast arrangement in the interior of the cap housing, and having connections for electrical connection of the mounting plate to the power supply leads and to the connecting contacts. The discharge vessel mount in this case comprises a plate (5) which is mounted in a further mount, with the further mount in turn being mounted on the housing of the cap. The further mount may be in the form of an enveloping bulb (2) or a reflector for the discharge vessel, or in the form of a closure cap (20) for the cap housing.

Abstract: A psuedostatic memory circuit is selected by a memory selection signal. A control circuit, in a first operating mode, carries out a refresh of the memory area at a refresh address after reception of the refresh request signal by generation of a refresh signal if the memory circuit is deselected or if, in the event of selection of the memory circuit by the memory selection signal, the access to the memory area is ended before the generation of a further refresh request signal. The control circuit, in a second operating mode, interrupts an access to the memory area for the writing and read-out of data and carries out a refresh of the memory area by generation of a refresh signal if the memory circuit is selected and a further refresh request signal is received before the ending of the access to the memory area.

Abstract: A calibration apparatus is provided for adjusting the relative phase between two signals received at a memory chip, the two signals being generated such that they are synchronized with one another in a controller and are transmitted to the memory chip via separate lines. The calibration apparatus comprises a measuring device, which is arranged in the memory chip and is designed for measuring the relative phase between the two received signals, and a feedback loop containing a phase-controlling correction device. The measuring device is designed for generating an item of control information indicating the deviation of the measured relative phase from a defined tolerance range. The correction device responds to the control information to compensate for the deviation. The correction device is arranged in the controller and is designed for influencing the relative phase between the two signals to be transmitted to the memory chip.

Abstract: The invention relates to a semiconductor memory module having a plurality of memory chips and at least one buffer chip, which drives clock signals and command and address signals to the memory chips and also drives data signals to, and receives them from, the memory chips via a module-internal clock, address, command and data signal bus. The buffer chip forms an interface to an external memory main bus and the memory chips are arranged in at least one row.

Abstract: The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and command and address signals to the memory chips and data signals to and from the memory chips via a clock, address, command and data bus inside the module and which forms an interface to an external primary memory bus. The semiconductor memory module has an even number of buffer chips arranged on it and all of the memory chips are connected to two respective buffer chips at least by one signal line type from a signal group and just to one of the two buffer chips by the remaining signal lines from the group.

Abstract: The invention relates to a semiconductor memory module having a plurality of memory chips arranged next to one another in a row. The memory module has a module-internal clock, command/address and data bus which transfers clock signal, command and address signals and also data signals from a memory controller device to the memory chips and data signals from the memory chips to the memory controller device. The memory module has respective clock, command/address and data signal lines. The clock signal lines comprise two differential clock signal lines which, at their end opposite to the memory controller device are either open or connected to one another by a short-circuiting bridge. The memory chips, during a write operation, synchronize the write data with the clock signal running from the memory controller device to the end of the clock signal line and, during a read operation, output the read data synchronously with the clock signal reflected from the open or short-circuited end of the clock signal lines.

Abstract: The invention relates to a semiconductor memory module having at least one memory chip and a buffer chip, which drives clock, address and command signals to the memory chip and drives data signals to, and receives them from, the memory chip via a module-internal clock, address, command and data bus. The buffer chip forms an interface to an external memory main bus. The data bus lines and/or the clock, command and address bus lines are respectively connected to the buffer chip at their two ends and are capable of being driven by the buffer chip from these two ends. Control means are being provided and set up in such a manner that they respectively match the directions of propagation of the data signals and of the clock, command and address signals on the corresponding bus lines during writing and reading.

Abstract: A memory module comprises a plurality of integrated memory components which are arranged on a carrier substrate. An access control circuit which is arranged separately from the memory components on the carrier substrate, is connected, on the input side, to terminals for supplying address and command signals and, on the output side, to the plurality of integrated memory components. The access control circuit is designed in such a manner that, when supplying an address signal, it receives an address for a memory access to a selected memory component; generates, from the address received, at least one column address and row address for accessing a bit line and word line of the selected memory component and transmits the addresses to the latter.

Abstract: The invention relates to an electric lamp (1) comprising at least one vessel (3) for producing and emitting visible electromagnetic radiation, a base (9) for securing and making electrical contact with the lamp (1) in a luminaire fitting, and a connecting part which connects the base to one of the remaining parts of the lamp (1). The connecting part is in this case in the form of a rotationally symmetrical rotary device (8) which makes it possible for the remaining parts of the lamp (1) to be rotated with respect to the base (9), when the base (9) is secured in the fitting, about the axis of the lamp (1).

Abstract: A method, system and protocol for a synchronous memory system. One embodiment of a system comprises: a memory control device; one or more memory modules in a main memory, with each memory module comprising one or more memory banks; a transfer bus for communication between the memory control device and the memory modules, where the transfer bus is in the form of a concatenated bus structure and comprises a plurality of parallel transfer lines; and where the memory control device is designed to generate commands comprising a plurality of command segments with a respective plurality of elements, and to transfer them to the memory modules using the transfer bus. The transfer bus is configured to transfer the elements of a command segment in parallel, and the commands each comprise a selection command segment for selecting one or more memory banks, with each of the memory banks having at least one uniquely associated element of the selection command segment.

Abstract: Methods and apparatus for allocating memory arrangement addresses to a buffer chip, during an initialization mode, for use in addressing one or more memory arrangements connected to the buffer chip are provided. A buffer circuit may receive first initialization data specifying a first set of available memory arrangement addresses and associate one or more of the first set of available memory arrangement addresses with the one or more memory arrangements connected to the buffer chip. The buffer circuit may also generate second initialization data specifying the set of available memory arrangement addresses available after the association. The second initialization data may be transmitted to another buffer circuit for use in address allocation or back to a memory access control unit.

Abstract: A remote control of a hearing aid is integrated into a case (1) of a wrist watch with wristband (3). A coil antenna (5) of the remote control is designed to generate a field similar to that of a dipole (P) which substantially runs in the direction of the wristband (3). The wrist watch remote control for the hearing aid provides a reliable communication link that is assured for the in-situ hearing aid.

Abstract: A memory module includes a plurality of integrated memory components are arranged on a mounting substrate and a refresh control circuit arranged separately from the memory components on the mounting substrate. The output of the refresh control circuit is connected to the plurality of integrated memory components. The refresh control circuit receives and processes address or command signals which have been generated outside the memory module; based on the access information obtained therefrom, independently generates a refresh command or a refresh command sequence for refreshing the contents of memory cells in a selected one of the memory components; and transmits the command or command sequence to the selected memory component. Refresh commands of this type no longer have to be generated by a memory controller.

Abstract: A circuit configuration has a transmitter unit connected to a first signal line and a receiver unit connected to a second signal line and is coupled to the transmission unit via a third signal line and a control line. The transmission unit receives and transmits a first bit group to be transmitted and a subsequent, second bit group to be transmitted. The transmission unit respectively identifies a signal state change between bits in the transmitted first bit group and corresponding bits in the received second bit group and determines the number of signal state changes. On the basis of the number thereof, the transmission unit transmits the second bit group to the receiver unit in unaltered or altered form, with altered transmission being indicated by a control signal. By influencing the number of charge reversal operations during signal transmission, the circuit configuration permits an overall reduction in current drawn.

Abstract: A memory module, which enables a module-internal, cross-chip electrical functional test of a plurality of integrated memory chips arranged on a printed circuit board of the memory module, includes a test device arranged separately from the memory chips on the printed circuit board. The test device relies on a clock signal provided by an external tester and generates the test signals required for carrying out the functional test and forwards the signals via control lines, address lines, data lines, and lines for the selection of individual memory chips to the latter. The partial integration of test functions into the test device enables a greater independence with respect to external electromagnetic interference influences without the space requirement of the memory module being increased overmuch.

Abstract: A memory circuit, in particular a psuedostatic memory circuit, is selected by a memory selection signal. The memory circuit has memory areas and a control circuit in order to refresh a memory area of the memory circuit in accordance with a refresh request signal. The control circuit, in a first operating mode, carries out a refresh of the memory area at a refresh address after reception of the refresh request signal by generation of a refresh signal if the memory circuit is deselected or if, in the event of selection of the memory circuit by the memory selection signal, the access to the memory area is ended before the generation of a further refresh request signal. The control circuit, in a second operating mode, interrupts an access to the memory area for the writing and read-out of data and carries out a refresh of the memory area by generation of a refresh signal if the memory circuit is selected and a further refresh request signal is received before the ending of the access to the memory area.

Abstract: A compact low-pressure discharge lamp (1) includes a discharge vessel (3) with electrodes and power supply leads (7), a discharge vessel mount (5) and a cap (12) which has a housing (13), connecting contacts (14) and a mounting plate (15) with a ballast apparatus (16), with the mounting plate (15) being fitted with the ballast arrangement (16) in the interior of the cap housing (13), and having connections for electrical connection of the mounting plate (15) to the power supply leads (7) and to the connecting contacts (14). The discharge vessel mount (5) has an essentially H-shaped cross section and includes a plate (4) with collars (9, 18) running on the edge of each side of the plate. Both the housing (13) of the cap (12) and the cover part, which is in the form of an enveloping bulb (2), a reflector or a closure cap, are mounted on this H-shaped discharge vessel mount (5).

Abstract: An integrated memory has address inputs for applying a row address or a column address and a latency value, and an instruction decoder with a signal input. The instruction decoder uses a signal applied to the signal input to determine whether the address applied to the address inputs is the row address or the column address. If a column address is applied, an evaluation unit which is connected downstream of the instruction decoder and has evaluation inputs which are connected to the address inputs, is used to apply a latency signal corresponding to the latency value to an output of the evaluation unit.

Abstract: A circuit configuration has a transmitter unit connected to a first signal line and a receiver unit connected to a second signal line and is coupled to the transmission unit via a third signal line and a control line. The transmission unit receives and transmits a first bit group to be transmitted and a subsequent, second bit group to be transmitted. The transmission unit respectively identifies a signal state change between bits in the transmitted first bit group and corresponding bits in the received second bit group and determines the number of signal state changes. On the basis of the number thereof, the transmission unit transmits the second bit group to the receiver unit in unaltered or altered form, with altered transmission being indicated by a control signal. By influencing the number of charge reversal operations during signal transmission, the circuit configuration permits an overall reduction in current drawn.

Abstract: Compact low-pressure discharge lamp The invention relates to a compact low-pressure discharge lamp (1) comprising a discharge vessel (3) with electrodes and power supply leads (7), a discharge vessel mount (5) and a cap (12) which comprises a housing (13), connecting contacts (14) and a mounting plate (15) with a ballast apparatus (16), with the mounting plate (15) being fitted with the ballast arrangement (16) in the interior of the cap housing (13), and having connections for electrical connection of the mounting plate (15) to the power supply leads (7) and to the connecting contacts (14). The discharge vessel mount (5) has an essentially H-shaped cross section and comprises a plate (4) with collars (9, 18) running on the edge of each side of the plate. Both the housing (13) of the cap (12) and the cover part, which is in the form of an enveloping bulb (2), a reflector or a closure cap, are mounted on this H-shaped discharge vessel mount (5).